Freescale Semiconductor MCF52277, Reference Manual

Page: 141 / 800

MCF52277 Reference Manual, Rev. 1
Freescale Semiconductor 8-1
Chapter 8
Power Management
8.1 Introduction
This chapter explains the low-power operation of the device.
8.1.1 Features
These features support low-power operation:
• Four operation modes: run, wait, doze, and stop
• Ability to shut down most peripherals independently
• Ability to shut down clocks to most peripherals independently
• Ability to run the device in low-frequency limp mode
• Ability to shut down the external FB_CLK pin
8.2 Memory Map/Register Definition
The power management programming model consists of registers from the SCM and CCM memory space:
Table 8-1. Power Management Memory Map
Address Register
Width
(bits)
Access Reset Value Section/Page
Supervisor Access Only Registers
1
1
User access to supervisor only address locations have no effect and result in a bus error
0xFC04_0013 Wakeup Control Register (WCR) 8 R/W 0x00 8.2.1/8-2
0xFC04_002C Peripheral Power Management Set Register (PPMSR) 8 W 0x00 8.2.2/8-3
0xFC04_002D Peripheral Power Management Clear Register (PPMCR) 8 W 0x00 8.2.3/8-4
0xFC04_0030 Peripheral Power Management High Register (PPMHR) 32 R/W 0x0000_0000 8.2.4/8-4
0xFC04_0034 Peripheral Power Management Low Register (PPMLR) 32 R/W 0x0000_0000 8.2.4/8-4
0xFC0A_0007 Low-Power Control Register (LPCR) 8 R/W 0x00 8.2.5/8-7
0xFC0A_0010 Miscellaneous Control Register (MISCCR)
2
2
The MISCCR and CDR registers are described in Chapter 9, “Chip Configuration Module (CCM).”
16 R/W See Section 10.3.5/10-11
0xFC0A_0012 Clock Divider Register (CDR)
2
16 R/W 0x0001 10.3.6/10-13