SIC63616-(Rev. 1.0) NO. P177
3240-0412
To avoid improper reloading, do not rewrite the reload data after an interrupt occurs until the counter
data is determined including the reloading period
➀
. Be especially careful when using the OSC1 (low-
speed clock) as the clock source of the programmable timer and the CPU is operating with the OSC3
(high-speed clock).
(6) The programmable timer count clock does not synch with the CPU clock. Therefore, the correct value
may not be obtained depending on the count data read and count-up timings. To avoid this problem,
the programmable timer count data should be read by one of the procedures shown below.
• Read the count data twice and verify if there is any difference between them.
• Temporarily stop the programmable timer when the counter data is read to obtain proper data.
Serial interface
(1) Perform data writing/reading to the data registers SD0–SD7 only while the serial interface is not run-
ning (i.e., the synchronous clock is neither being input or output).
(2) As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be per-
formed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through
data writing/reading on data registers SD0–SD7.) In addition, be sure to enable the serial interface with
the ESIF register before setting the trigger.
Supply trigger only once every time the serial interface is placed in the RUN state. Refrain from per-
forming trigger input multiple times, as leads to malfunctioning. Moreover, when the synchronous
clock SCLK is external clock, start to input the external clock after the trigger.
(3) Setting of the input/output permutation (MSB first/LSB first) with the SDP register should be done
before setting data to SD0–SD7.
(4) Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when the pro-
grammable timer is used as the clock source or the serial interface is used in slave mode.
Sound generator
(1) Since it generates a buzzer signal that is out of synchronization with the BZE register, hazards may at
times be produced when the signal goes on/off due to the setting of the BZE register.
(2) The one-shot output is only valid when the normal buzzer output is off (BZE = "0") and will be invalid
when the normal buzzer output is on (BZE = "1").
Integer multiplier
An operation process takes 10 CPU clock cycles (5 bus cycles) after writing to the calculation mode
select register CALMD until the operation result is set to the destination register DRH/DRL and the
operation flags. While this operation process, do not read/write from/to the destination register DRH/
DRL and do not read NF/VF/ZF.
R/f converter
(1) When an error interrupt occurs, reset the overflow flag (OVMC or OVTC) by writing "1". The same error
interrupt will occur again if the overflow flag is not reset.
(2) When setting the measurement counter or time base counter, always write 5 words of data continu-
ously in order from the lower address (FF62H
→
FF63H
→
FF64H
→
FF65H
→
FF66H, FF67H
→
FF68H
→
FF69H
→
FF6AH
→
FF6BH). Furthermore, an LD instruction should be used for writing data to the
measurement counter and a read-modify-write instruction (AND, OR, ADD, SUB, etc.) cannot be used.
If data other than low-order 4 bits is written, the counter cannot be set to the desired value.
(3) Voltage deviation of reference/sensor oscillation frequencies of the R/f converter becomes remarkable
especially at 2.0V or under, so use this after evaluation. Voltage deviation of reference/sensor oscillation
frequencies of the R/f converter may increase due to board resistances and capacitances of set environ-
ment.
