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Epson S1C63616, Technical Manual

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SIC63616-(Rev. 1.0) NO. P144

3240-0412

4.12.4 Division mode

To perform a division, set the divisor to the source register (SR) and the dividend to the destination register 
(DRH and DRL), then write "1" to the calculation mode select register (CALMD). The division takes 10 CPU 
clock cycles from writing "1" to CALMD until the quotient is loaded into the low-order 8 bits (DRL) of the 
destination register and the remainder is loaded into the high-order 8 bits (DRH) of the destination register. 
At the same time the result is loaded, the operation flags (NF, VF and ZF) are updated.
However, when an overflow results (if the quotient exceeds the 8-bit range), the destination register (DRH 
and DRL) does not change its contents as it maintains the dividend.
The following shows the conditions that change the operation flag states and examples of division.

N flag:

 Set when the MSB of DRL is "1" and reset when it is "0".

V flag:

 Set when the quotient exceeds the 8-bit range and reset when it is within the 8-bit range.

Z flag:

 Set when the 8-bit value in DRL is 00H and reset when it is not 00H.

<Examples of division>

  DRH/DRL (dividend)  SR (divisor)  DRL (quotient)  DRH (remainder)  NF  VF  ZF

 

1A16H 

64H 

42H 

4EH 

0 

0 

0

 

332CH 

64H 

83H 

00H 

1 

0 

0

 

0000H 

58H 

00H 

00H 

0 

0 

1

 

2468H 

13H 

68H 

24H 

1 

1 

0

In the example of "2468H" ÷ "13H" shown above, DRH/DRL maintains the dividend because the quotient 
overflows the 8-bit. To get the correct results when an overflow has occurred, perform the division with two 
steps as shown below.

1.  Divide the high-order 8 bits of the dividend (24H) by the divisor (13H) and then store the quotient (01H) 

to memory.

 

DRH/DRL (dividend)  SR (divisor)  DRL (quotient)  DRH (remainder)  NF  VF  ZF

 

0024H 

13H 

01H 

11H 

0 

0 

0

2.  Keep the remainder (11H) in DRH and load the low-order 8 bits of the dividend (68H) to DRL, then 

perform division again.

 

DRH/DRL (dividend)  SR (divisor)  DRL (quotient)  DRH (remainder)  NF  VF  ZF

 

1168H 

13H 

EAH 

0AH 

1 

0 

0

The correct result is obtained as the quotient = 01EAH (the first and second results of DRL are merged) 
and the remainder = 0AH. However, since the operation flags (NF/VF/ZF) are changed in each step, they 
cannot indicate the states according to the final operation results.

Note:  Make sure that the division results are correct using software as the hardware does not check.

Summary of Contents for S1C63616

Page 1: ...S1C63616 Technical Manual Rev 1 0 ...

Page 2: ...reover no license to any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exch...

Page 3: ... 99 Specs not fixed Specification Package D die form F QFP B BGA Model number Model name C microcomputer digital products Product classification S1 semiconductor Development tools S5U1 C 17000 H2 1 Packing specifications 00 standard packing Version 1 Version 1 Tool type Hx ICE Dx Evaluation board Ex ROM emulation board Mx Emulation memory for external ROM Tx A socket for mounting Cx Compiler packa...

Page 4: ...________________14 3 1 CPU 14 3 2 Code ROM 14 3 3 RAM 14 3 4 Data ROM 15 chapter 4 Peripheral Circuits and Operation________________________________16 4 1 Memory Map 16 4 2 Power Control 32 4 2 1 Configuration of power supply circuit 32 4 2 2 Controlling the power supply voltage booster halver and voltage regulators 33 4 2 3 Heavy load protection function 34 4 2 4 I O memory for power control 34 4...

Page 5: ... 4 8 2 Controlling clock manager 84 4 8 3 Counter and prescaler 85 4 8 4 Capture buffer and hold function 85 4 8 5 Stopwatch timer RUN STOP and reset 86 4 8 6 Direct input function and key mask 87 4 8 7 Interrupt function 90 4 8 8 I O memory of stopwatch timer 92 4 8 9 Programming notes 96 4 9 Programmable Timer 97 4 9 1 Configuration of programmable timer 97 4 9 2 Controlling clock manager 100 4 ...

Page 6: ...nterrupt function 154 4 13 6 Continuous oscillation function 156 4 13 7 I O memory of R f converter 156 4 13 8 Programming notes 160 4 14 SVD Supply Voltage Detection Circuit 161 4 14 1 Configuration of SVD circuit 161 4 14 2 SVD operation 161 4 14 3 I O memory of SVD circuit 162 4 14 4 Programming notes 162 4 15 Interrupt and HALT SLEEP 163 4 15 1 Interrupt factor 165 4 15 2 Interrupt mask 166 4 ...

Page 7: ..._________________205 A 1 Names and Functions of Each Part 205 A 1 1 S5U1C63000P6 205 A 1 2 S5U1C6F632P2 208 A 2 Connecting to the Target System 210 A 3 Downloading to S5U1C63000P6 214 A 3 1 Downloading Circuit Data 1 when new ICE S5U1C63000H2 S5U1C63000H6 is used 214 A 3 2 Downloading Circuit Data 2 when previous ICE S5U1C63000H1 is used 215 A 4 Usage Precautions 216 A 4 1 Operational precautions ...

Page 8: ...incorporated 1 Shared with 4 serial I F I O pins 4 R f converter I O pins and 3 special output pins 2 Serial interface 1 port 8 bit clock synchronous system LCD driver 40 segments 32 commons 48 segments 24 commons or 56 segments 16 commons 2 Time base counter Clock timer Stopwatch timer 1 1000 sec with direct key input function Programmable timer 16 bit timer 4 ch each 16 bit timer is configurable...

Page 9: ...D REF1 RFIN1 BZ P03 TOUT_A P13 SIN P22 SOUT P21 SRDY SS P23 SCLK P20 Core CPU S1C63000 Code ROM 16 384 words 13 bits System Reset Control Interrupt Generator OSC RAM 2 048 words 4 bits Data ROM 2 048 words 4 bits LCD Controller Driver Power Controller SVD Watchdog Timer Clock Timer Stopwatch Timer Programmable Timer Sound Generator Integer Multiplier Test R f Converter I O Port Serial Interface Fi...

Page 10: ...EVIN_A P13 TOUT_A P20 SCLK P21 SOUT P22 SIN P23 SRDY SS FOUT P40 P41 EVIN_B P42 EVIN_C P43 EVIN_D RESET TEST V OSC V D1 N C N C N C 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 OSC2 OSC1 VSS OSC4 OSC3 VDD VC1 VC2 VC3 VC4 VC5...

Page 11: ..._A P20 SCLK P21 SOUT P22 SIN P23 SRDY SS FOUT P40 P41 EVIN_B P42 EVIN_C P43 EVIN_D RESET TEST N C N C N C N C N C V OSC N C V D1 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 OSC2 OSC1 VSS OSC4 ...

Page 12: ...input pin software switch I O port or event counter input pin software switch I O port or programmable timer output pin software switch I O port or serial I F clock I O pin software switch I O port or serial I F data output pin software switch I O port or serial I F data input pin software switch I O port serial I F ready signal output SS signal input or FOUT clock output pin software switch I O p...

Page 13: ... P43 Refer to Section 4 5 2 Mask option for details 5 Output specification of the I O port This option is used to select either complementary output or P channel open drain output as the output cell type of each I O port P00 P03 P10 P13 P20 P23 P40 P43 Refer to Section 4 5 2 Mask option for details 6 Multiple key entry reset function by simultaneous high input to the P1x ports This option is used ...

Page 14: ...1 Use 2 Not Use P12 1 Use 2 Not Use P13 1 Use 2 Not Use P20 1 Use 2 Not Use P21 1 Use 2 Not Use P22 1 Use 2 Not Use P23 1 Use 2 Not Use P40 1 Use 2 Not Use P41 1 Use 2 Not Use P42 1 Use 2 Not Use P43 1 Use 2 Not Use 5 I O PORT OUTPUT SPECIFICATION P00 1 Complementary 2 Pch Open Drain P01 1 Complementary 2 Pch Open Drain P02 1 Complementary 2 Pch Open Drain P03 1 Complementary 2 Pch Open Drain P10 ...

Page 15: ... KEY ENTRY RESET COMBINATION 1 Not Use 2 Use P10 P11 3 Use P10 P11 P12 4 Use P10 P11 P12 P13 7 MULTIPLE KEY ENTRY RESET TIME AUTHORIZE 1 Not Use 2 Use 8 LCD DRIVING POWER 1 1 5 Bias VC2 Reference 2 1 4 Bias VC2 Reference 3 1 4 Bias VC1 Reference ...

Page 16: ...r halver operates in boost mode 4 HLON is prohibited from use 1 2 Power supply voltage booster halver Oscillation system voltage regulator Internal voltage regulator OSC3 oscillation circuit Internal circuits OSC1 oscillation circuit DBON VCSEL HLON External power supply VDD CF CG VD2 VD1 VOSC VC1 VC2 VC3 VC4 VC5 CA CB CC CD CE VSS VDD VD1 VD2 VOSC LCD driver circuit LCD system voltage regulator 3...

Page 17: ... 5 5 V 1 6 V to 5 5 V when the VC1 reference LCD drive power option is selected In this case the power supply voltage booster halver can be turned off The S1C63616 allows software to control the power supply voltage booster halver and to select the power source of the voltage regulator Refer to Section 4 2 Power Control for details Internal voltage regulator The internal voltage regulator generate...

Page 18: ...y setting the reset terminal to a low level VSS and the CPU starts operating The reset input signal is maintained by the RS latch and becomes the internal initial reset signal The RS latch is designed to be released by a 16 Hz signal high that is divided by the OSC1 clock Therefore in normal operation a maximum of 16 396 fOSC1 seconds 500 msec when fOSC1 32 768 kHz is needed until the internal ini...

Page 19: ...t if that time is the defined time 1 to 2 sec or more If using this function make sure that the specified ports do not go high at the same time during ordinary operation 2 2 3 Internal register at initial resetting Initial reset initializes the CPU as shown in Table 2 2 3 1 The registers and flags which are not initialized by initial reset should be initialized in the program if neces sary In part...

Page 20: ...ulled down P03 Input pulled down P10 Input pulled down P11 Input pulled down P12 Input pulled down P13 Input pulled down P20 Input pulled down P21 Input pulled down P22 Input pulled down P23 Input pulled down P40 Input pulled down P41 Input pulled down P42 Input pulled down P43 Input pulled down TOUT TOUT_A FOUT FOUT BZ BZ Master SCLK O SOUT O SIN I Slave SCLK I SOUT O SIN I SRDY O SS I R f conver...

Page 21: ...OM 3 3 RAM The RAM is a data memory for storing various kinds of data and has a capacity of 2 048 words 4 bits The RAM area is assigned to addresses 0000H to 07FFH on the data memory map Addresses 0100H to 01FFH are 4 bit 16 bit data accessible areas and in other areas it is only possible to access 4 bit data When pro gramming keep the following points in mind 1 Part of the RAM area is used as a s...

Page 22: ...ack area 4 bit access area Data area 4 16 bit access area SP1 stack area 0000H 0800H 8000H 8800H F000H FF00H FFFFH RAM Unused area Unused area Unused area Data ROM I O memory area Display memory area Fig 3 3 1 Configuration of data RAM 3 4 Data ROM The data ROM is a mask ROM for loading various static data such as a character generator and has a ca pacity of 2 048 words 4 bits The data ROM is assi...

Page 23: ... word peripheral I O memory Figure 4 1 1 shows the overall memory map of the S1C63616 and Table 4 1 1 the peripheral circuits I O space memory maps 0000H 0800H 8000H 8800H F000H FF00H FFFFH Display memory area Unused area F000H F36FH FF00H FFFFH Peripheral I O area RAM area Unused area Unused area Unused area Data ROM area I O memory area Display memory area Fig 4 1 1 Memory map Note Memory is not...

Page 24: ...R W FOUT3 FOUT2 FOUT1 FOUT0 0 0 0 0 FOUT frequency selection FOUT3 0 Frequency FOUT3 0 Frequency FOUT3 0 Frequency 0 Off 1 fOSC1 256 2 fOSC1 64 3 fOSC1 32 4 fOSC1 16 5 fOSC1 4 6 fOSC1 2 11 fOSC3 16 7 fOSC1 12 fOSC3 8 8 fOSC3 256 13 fOSC3 4 9 fOSC3 64 14 fOSC3 2 10 fOSC3 32 15 fOSC3 0 Off External SIFCKS2 0 Frequency 1 fOSC1 2 fOSC1 2 3 fOSC1 4 4 PT1 SIFCKS2 0 Frequency 5 fOSC3 6 fOSC3 2 7 fOSC3 4 ...

Page 25: ...3 PTPS42 PTPS41 PTPS40 0 0 0 0 Programmable timer 4 count clock frequency selection PTPS43 40 Frequency PTPS43 40 Frequency PTPS43 40 Frequency 0 Off 1 fOSC1 256 2 fOSC1 64 3 fOSC1 32 4 fOSC1 16 5 fOSC1 4 6 fOSC1 2 11 fOSC3 16 7 fOSC1 12 fOSC3 8 8 fOSC3 256 13 fOSC3 4 9 fOSC3 64 14 fOSC3 2 10 fOSC3 32 15 fOSC3 FF1DH PTPS53 PTPS52 PTPS51 PTPS50 R W PTPS53 PTPS52 PTPS51 PTPS50 0 0 0 0 Programmable t...

Page 26: ... purpose register when TOUT_A is used P12 I O port data P11 I O port data P10 I O port data FF25H IOC13 IOC12 IOC11 IOC10 R W IOC13 IOC12 IOC11 IOC10 0 0 0 0 Output Output Output Output Input Input Input Input P13 I O control register functions as a general purpose register when TOUT_A is used P12 I O control register P11 I O control register P10 I O control register Address Comment D3 D2 Register...

Page 27: ...ister SIN pull down control register when SIF is used P21 pull down control register functions as a general purpose register when SIF SOUT is used P20 pull down control register SCLK I pull down control register when SIF slave is used functions as a general purpose register when SIF master is used PUL23 PUL22 PUL21 PUL20 FF2BH R W P23 input interface level select register SS input I F level select...

Page 28: ...CP12 PCP11 PCP10 R W PCP13 PCP12 PCP11 PCP10 1 1 1 1 P40 P43 interrupt polarity select register FF3EH SIP13 SIP12 SIP11 SIP10 R W SIP13 SIP12 SIP11 SIP10 0 0 0 0 Enable Enable Enable Enable Disable Disable Disable Disable P40 P43 interrupt select register D3 D2 D1 D0 Name Init 1 1 0 Address Comment Register FF30H P43 P42 P41 P40 R W P43 P42 P41 P40 1 1 1 1 High High High High Low Low Low Low P40 P...

Page 29: ... stop writing 1 shot buzzer trigger writing 1 shot buzzer status reading 1 shot buzzer pulse width setting FF48H R R W FF49H 0 DKM2 DKM1 DKM0 0 3 DKM2 DKM1 DKM0 2 0 0 0 R W W R FF4AH LCURF CRNWF SWRUN SWRST LCURF CRNWF SWRUN SWRST 3 0 0 0 Reset Request Renewal Run Reset No No Stop Invalid Lap data carry up request flag Capture renewal flag Stopwatch timer Run Stop Stopwatch timer reset writing SWD...

Page 30: ...23 function selection MC3 MC2 MC1 MC0 2 2 2 2 Measurement counter MC0 MC3 LSB R W R W FF62H MC3 MC2 MC1 MC0 MC7 MC6 MC5 MC4 2 2 2 2 Measurement counter MC4 MC7 FF63H MC7 MC6 MC5 MC4 FF60H RFCNT RFOUT ERF1 ERF0 R W RFCNT RFOUT ERF1 ERF0 0 0 0 0 Continue Enable Normal Disable Continuous oscillation enable RFOUT enable R f conversion selection 0 I O 1 Ch 0 DC 2 Ch 1 AC 3 Ch 1 DC ERF1 0 R f conversion...

Page 31: ...RUN0 2 0 2 0 Reset Run Reset Run Invalid Stop Invalid Stop W R W W R W FF82H PTRST1 PTRUN1 PTRST0 PTRUN0 TC11 TC10 TC9 TC8 2 2 2 2 R W FF69H TC11 TC10 TC9 TC8 TC7 TC6 TC5 TC4 2 2 2 2 R W FF68H TC7 TC6 TC5 TC4 Time base counter TC12 TC15 MSB Time base counter TC16 TC19 Low order 8 bit destination register low order 4 bits LSB MSB Low order 8 bit destination register high order 4 bits High order 8 b...

Page 32: ... W FF90H MOD16_B EVCNT_B FCSEL_B PLPUL_B PTSEL3 PTSEL2 CHSEL_B PTOUT_B 0 0 0 0 PWM PWM 1 1 Normal Normal 0 0 R W FF91H PTSEL3 PTSEL2 CHSEL_BPTOUT_B MSB Programmable timer 1 reload data low order 4 bits LSB MSB Programmable timer 1 reload data high order 4 bits LSB MSB Programmable timer 0 data low order 4 bits LSB MSB Programmable timer 0 data high order 4 bits LSB MSB Programmable timer 0 compare...

Page 33: ...ogrammable timer 2 compare data low order 4 bits LSB MSB Programmable timer 3 data low order 4 bits LSB MSB Programmable timer 3 data high order 4 bits LSB MSB Programmable timer 2 compare data high order 4 bits LSB MSB Programmable timer 3 compare data low order 4 bits LSB MSB Programmable timer 3 compare data high order 4 bits LSB Address Comment Register Programmable timer 3 reset reload Progra...

Page 34: ...0 0 0 0 R W FFA4H RLD43 RLD42 RLD41 RLD40 RLD47 RLD46 RLD45 RLD44 0 0 0 0 R W FFA5H RLD47 RLD46 RLD45 RLD44 CD57 CD56 CD55 CD54 0 0 0 0 MSB Programmable timer 5 reload data low order 4 bits LSB MSB Programmable timer 5 reload data high order 4 bits LSB MSB Programmable timer 4 data low order 4 bits LSB MSB Programmable timer 4 data high order 4 bits LSB MSB Programmable timer 4 compare data low or...

Page 35: ...4H RLD63 RLD62 RLD61 RLD60 RLD67 RLD66 RLD65 RLD64 0 0 0 0 R W FFB5H RLD67 RLD66 RLD65 RLD64 CD73 CD72 CD71 CD70 0 0 0 0 R W FFBEH CD73 CD72 CD71 CD70 MSB Programmable timer 7 reload data low order 4 bits LSB MSB Programmable timer 7 reload data high order 4 bits LSB MSB Programmable timer 6 data low order 4 bits LSB MSB Programmable timer 6 data high order 4 bits LSB MSB Programmable timer 6 comp...

Page 36: ...ter sensor oscillate completion General purpose register General purpose register Interrupt mask register Programmable timer 0 underflow Interrupt mask register Programmable timer 0 compare match General purpose register General purpose register Interrupt mask register Programmable timer 1 underflow Interrupt mask register Programmable timer 1 compare match General purpose register General purpose...

Page 37: ...g Programmable timer 7 underflow Interrupt factor flag Programmable timer 7 compare match Unused Unused Unused Interrupt factor flag Serial interface Interrupt factor flag Key input interrupt 3 P13 Interrupt factor flag Key input interrupt 2 P12 Interrupt factor flag Key input interrupt 1 P11 Interrupt factor flag Key input interrupt 0 P10 Interrupt factor flag Key input interrupt 7 P43 Interrupt ...

Page 38: ...D0 Name Init 1 1 0 Interrupt factor flag Stopwatch direct RUN Interrupt factor flag Stopwatch direct LAP Interrupt factor flag Stopwatch timer 1 Hz Interrupt factor flag Stopwatch timer 10 Hz Interrupt factor flag Clock timer 16 Hz Interrupt factor flag Clock timer 32 Hz Interrupt factor flag Clock timer 64 Hz Interrupt factor flag Clock timer 128 Hz Interrupt factor flag Clock timer 1 Hz Interrup...

Page 39: ...C3 VC4 VC5 CA CB CC CD CE VSS VDD VD1 VD2 VOSC LCD driver circuit LCD system voltage regulator 3 4 VDD Fig 4 2 1 1 Built in power supply circuit Power supply voltage booster halver The power supply voltage booster halver generates the operating voltage VD2 for the voltage regula tor LCD system voltage regulator The S1C63616 allows software to control the power supply voltage booster halver and to ...

Page 40: ...ption is selected the LCD system voltage regulator must be driven with a 2 5 V or more power voltage Therefore they can be driven with VDD if the supply voltage VDD is 2 5 V or more When the supply voltage VDD less than 2 5 V is used drive the power supply volt age booster halver in boost mode to generate VD2 and use it to drive the LCD system voltage regulator Use VCSEL to select the power source...

Page 41: ...ty Note Current consumption increases in heavy load protection mode therefore do not set heavy load protection mode with software if unnecessary 4 2 4 I O memory for power control Table 4 2 4 1 shows the I O address and the control bits for power control Table 4 2 4 1 Power control bits Address Comment D3 D2 Register D1 D0 Name Init 1 1 0 FF03H VCHLMOD VDHLMOD General LPWR R W VCHLMOD VDHLMOD Gene...

Page 42: ... boost mode and VCSEL to 1 driving with VD2 if the supply voltage VDD exceeds 2 5 V as it may cause damage of the IC LPWR LCD system voltage regulator On Off register FF03H D0 Turns the LCD system voltage regulator on and off When 1 is written On When 0 is written Off Reading Valid When 1 is written to LPWR the LCD system voltage regulator goes on and generates the LCD drive voltages When 0 is wri...

Page 43: ...reases current consumption compared with normal operation mode Therefore do not set heavy load protection mode unless it is necessary At initial reset this register is set to 0 4 2 5 Programming notes 1 When the power supply voltage booster halver is turned on the VD2 output voltage requires about 1 msec to stabilize Do not switch the power source for the voltage regulator LCD system voltage regul...

Page 44: ...tes the non maskable interrupt when the last stage of the counter 0 25 Hz overflows Watchdog timer reset processing in the program s main routine enables detection of program overrun such as when the main routine s watchdog timer processing is bypassed Ordinarily this routine is incorporated where periodic processing takes place just as for the timer interrupt routine The watchdog timer operates i...

Page 45: ... to WDRST the watchdog timer is reset and restarts immediately after that When 0 is written no operation results This bit is dedicated for writing and is always 0 for reading WDEN Watchdog timer enable register FF01H D1 Selects whether the watchdog timer is used enabled or not disabled When 1 is written Enabled When 0 is written Disabled Reading Valid When 1 is written to the WDEN register the wat...

Page 46: ... Oscillation system block diagram At initial reset OSC1 oscillation circuit is selected as the CPU operating clock source The S1C63616 allows the software to turn the OSC3 oscillation circuit on and off and to switch the system clock between OSC3 and OSC1 The OSC3 oscillation circuit is used when the CPU and some peripheral circuits need high speed operation Otherwise use the OSC1 oscillation circ...

Page 47: ...SC1 terminal and VSS 4 4 4 OSC3 oscillation circuit The OSC3 oscillation circuit generates the system clock to run the CPU and some peripheral circuits at high speed This oscillation circuit stops when the SLP instruction is executed or the OSCC register is set to 0 The oscillator type can be selected from ceramic or CR by mask option Figure 4 4 4 1 shows the configuration of the OSC3 oscillation ...

Page 48: ...SC3 to OSC1 the OSC3 oscillation circuit can be turned off immediately When switching the clock from OSC3 to OSC1 CLKCHG 1 0 be sure to switch OSC3 oscillation off with separate instructions Using a single instruction to process simultaneously can cause a malfunction of the CPU Figure 4 4 5 1 indicates the status transition diagram for the clock changeover RESET OSCC 1 OSCC 0 CLKCHG 1 CLKCHG 0 ON ...

Page 49: ... On Off Unused Unused 1 Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read OSCC OSC3 oscillation control register FF00H D2 Turns the OSC3 oscillation circuit on and off When 1 is written OSC3 oscillation On When 0 is written OSC3 oscillation Off Reading Valid When it is necessary to operate the CPU at high speed set OSCC to 1 At other times set it to 0 to reduce...

Page 50: ...ficient waiting time once the OSC3 oscillation goes on The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts Refer to the oscillation start time example indicated in Chapter 7 Electrical Characteristics 3 When switching the clock from OSC3 to OSC1 be sure to switch OSC3 oscillation off with separate instructions Using a single instruction to...

Page 51: ...ly Refer to Output Terminals in Section 5 3 Precautions on Mounting for more information Each I O port terminal provides an internal pull down resistor The mask option allows selection of the pull down resistor to be connected or disconnected in 1 bit units When Use is selected by mask option the port suits input from the push switch key matrix and so forth When Not use is selected the port can be...

Page 52: ...or peripheral function is used the input output direction of the port is automatically configured by switching the terminal function For controlling the serial interface R f converter BZ output stopwatch timer and event counter refer to 4 10 Serial Interface 4 13 R f Converter 4 11 Sound Generator 4 8 Stopwatch Timer and 4 9 Programmable Timer Note Before the port function is configured the circui...

Page 53: ...red with a CMOS level input interface When SMTxx is set to 1 the port is configured with a CMOS Schmitt level input interface P0x is the fixed setting for CMOS Schmitt level At initial reset all the ports are configured with a CMOS Schmitt level interface The input interface level select register of the port that is set for a peripheral output R f converter input output or special output see Table...

Page 54: ... ineffective while the TOUT_A sig nal is being output When PTOUT_A is set to 0 the port is configured as a general purpose DC input output port The TOUT_A signal is generated from the underflow and compare match signals of a programmable timer Refer to Section 4 9 Programmable Timer for controlling the clock output and frequency Since the TOUT_A signal is generated asynchronously from the PTOUT_A ...

Page 55: ...on before starting FOUT output The oscillation start time will vary somewhat depending on the oscillator and on the externally attached parts Refer to the oscillation start time example indicated in Chapter 7 Electrical Characteristics Since the FOUT signal is generated asynchronously from the FOUT0 FOUT3 registers a hazard of a 1 2 cycle or less is generated when the signal is turned on or off by...

Page 56: ...ss Interrupt polarity select register PCP00 Noise rejector MUX Interrupt select register SIP00 Interrupt factor flag IK00 Address Interrupt mask register EIK00 Address Noise reject select register NRSP01 00 P10 P11 P12 P13 Sleep cancellation Interrupt request Address Address Address Address Interrupt polarity select register PCP10 Noise rejector MUX Interrupt select register SIP10 Interrupt factor...

Page 57: ...ed and no interrupt is generated to the CPU However SLEEP mode can be cancelled regardless of the interrupt mask register set ting The key input interrupt circuit has a noise rejector to avoid unnecessary interrupt generation due to noise or chattering This noise rejector allows selection of a noise reject frequency from among three types shown in Table 4 5 7 1 Use the NRSP01 and NRSP00 registers ...

Page 58: ...tions as a general purpose register when R f or BZ is used P02 I O control register functions as a general purpose register when R f is used P01 I O control register functions as a general purpose register when R f is used P00 I O control register functions as a general purpose register when R f is used FF24H P13 TOUT_A P12 P11 P10 R W P13 P12 P11 P10 1 1 1 1 High High High High Low Low Low Low P1...

Page 59: ...ral purpose register when SIF is used P21 I O control register functions as a general purpose register when SIF is used P20 I O control register functions as a general purpose register when SIF is used IOC23 IOC22 IOC21 IOC20 FF2AH R W PUL23 PUL22 PUL21 PUL20 1 1 1 1 On On On On Off Off Off Off P23 pull down control register SS pull down control register when SIF slave SS is used functions as a ge...

Page 60: ...MOS CMOS CMOS P40 P43 input interface level select register FF3CH SIP03 SIP02 SIP01 SIP00 R W SIP03 SIP02 SIP01 SIP00 0 0 0 0 Enable Enable Enable Enable Disable Disable Disable Disable P10 P13 interrupt select register FF30H P43 P42 P41 P40 R W P43 P42 P41 P40 1 1 1 1 High High High High Low Low Low Low P40 P43 I O port data FF31H IOC43 IOC42 IOC41 IOC40 R W IOC43 IOC42 IOC41 IOC40 0 0 0 0 Output...

Page 61: ...60H RFCNT RFOUT ERF1 ERF0 R W RFCNT RFOUT ERF1 ERF0 0 0 0 0 Continue Enable Normal Disable Continuous oscillation enable RFOUT enable R f conversion selection 0 I O 1 Ch 0 DC 2 Ch 1 AC 3 Ch 1 DC ERF1 0 R f conversion ENCS 0 1 1 Slave SMOD 0 P23 I O SS SRDY Master SMOD 1 P23 I O I O Prohibited ESREADY x 0 1 MOD16_A EVCNT_A FCSEL_A PLPUL_A 0 0 0 0 16 bits Event ct With NR 8 bits Timer No NR R W FF80...

Page 62: ... P13 Interrupt factor flag Key input interrupt 2 P12 Interrupt factor flag Key input interrupt 1 P11 Interrupt factor flag Key input interrupt 0 P10 Interrupt factor flag Key input interrupt 7 P43 Interrupt factor flag Key input interrupt 6 P42 Interrupt factor flag Key input interrupt 5 P41 Interrupt factor flag Key input interrupt 4 P40 FFFBH IK03 IK02 IK01 IK00 R W IK03 IK02 IK01 IK00 0 0 0 0 R...

Page 63: ...2 EVCNT_C PTM4 counter mode select register FFA0H D2 EVCNT_D PTM6 counter mode select register FFB0H D2 Selects a counter mode for programmable timer 0 2 4 6 When 1 is written Event counter mode When 0 is written Timer mode Reading Valid When 1 is written to the EVCNT_A B C D register programmable timer 0 2 4 6 is placed into event counter mode In this mode P12 P41 P42 P43 is used as an external c...

Page 64: ...en fetching input data set an appropriate wait time Particular care needs to be taken of the key scan during key matrix configuration Make this waiting time the amount of time or more calculated by the following expression 10 C R C terminal capacitance 5 pF parasitic capacitance pF R pull down resistance 375 kΩ Max IOC00 IOC03 P0 port I O control register FF21H IOC10 IOC13 P1 port I O control regi...

Page 65: ...configured with a CMOS Schmitt level input interface When 0 is written the port is configured with a CMOS level input interface P0x is the fixed setting for CMOS Schmitt level At initial reset these registers are set to 1 SIP00 SIP03 P1 port interrupt select register FF3CH SIP10 SIP13 P4 port interrupt select register FF3EH Selects the ports used for the key input interrupt from P10 P13 and P40 P4...

Page 66: ...et to 0 However enable the key input interrupt using the corresponding interrupt mask register before executing the SLP instruction to execute the key input interrupt handler routine after SLEEP status is released At initial reset these registers are set to 0 IK00 IK03 Key input interrupt 0 3 factor flag FFFBH IK10 IK13 Key input interrupt 4 7 factor flag FFFCH These flags indicate the occurrence ...

Page 67: ...utput When 1 is written Buzzer output On When 0 is written Buzzer output Off Reading Valid When 1 is written to BZE the BZ signal is output from the P03 terminal When 0 is written P03 is used as a general purpose DC input output port At initial reset this register is set to 0 BZSHT One shot buzzer trigger status FF45H D1 Controls the one shot buzzer output When writing When 1 is written Trigger Wh...

Page 68: ...EEP status can only be done by generation of a key input interrupt factor There fore when using the SLEEP function it is necessary to set the interrupt select register SIPxx 1 of the port to be used for releasing SLEEP status before executing the SLP instruction Furthermore enable the key input interrupt using the corresponding interrupt mask register EIKxx 1 before executing the SLP instruction t...

Page 69: ... LC3 LC2 LC1 LC0 LCD driver VC1 VC5 Display memory Clock manager VDD VD2 LPAGE VCSEL LDUTY2 LDUTY1 LDUTY0 DSPC1 DSPC0 VCCKS1 VCCKS0 FLCKS1 FLCKS0 DBON OSC1 Oscillation circuit Power supply voltage booster halver Fig 4 6 1 1 Configuration of LCD driver and drive power supply VC2 reference 1 5 bias VC1 VD2 VC3 VC4 VC5 CA CB CC CD CE CF CG COM0 COM15 SEG0 SEG55 VSS LCD system voltage regulator VC2 LC...

Page 70: ...ed TYPE 2 VC2 reference 1 4 bias VDD 1 6 to 2 5 V power supply voltage booster halver is used VDD 2 5 to 5 5 V power supply voltage booster halver is not used TYPE 3 VC1 reference 1 4 bias VDD 1 6 to 5 5 V power supply voltage booster halver is not used Select one from three types according to the supply voltage and the LCD panel characteristics The LCD drive voltages are generated by boosting hal...

Page 71: ... the boost clock supplied from the clock manager for boosting halving the voltage The clock supply is controlled by the VCCKS0 VCCKS1 register Set VCCKS to 01B before writing 1 to LPWR When LCD display is not necessary stop the clock supply by setting VCCKS to 00B to reduce power consumption Table 4 6 2 2 Controlling boost clock VCCKS1 1 0 0 Boost clock control Prohibited On 2 kHz Off VCCKS0 1 0 N...

Page 72: ...el to be used The frame frequency is determined by the selected duty and the clock supplied from the clock manager The clock to be supplied 8 Hz to 32 Hz can be selected using the FLCKS0 FLCKS1 register Selecting a low frame frequency can reduce current consumption Note The frame frequency affects the display quality therefore it should be determined after the display quality is evaluated using th...

Page 73: ... 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SEG0 1 2 3 4 VC5 VC4 VC3 VC2 VC1 V GND SS VC5 VC4 VC3 VC2 VC1 V GND SS VC1 VC2 VC3 VC4 VC5 VC1 VC2 VC3 VC4 VC5 VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS 32 Hz Fig 4 6 3 1 Drive waveform for 1 32 duty FLCKS 00B ...

Page 74: ...9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SEG0 1 2 3 4 VC5 VC4 VC3 VC2 VC1 V GND SS VC5 VC4 VC3 VC2 VC1 V GND SS VC1 VC2 VC3 VC4 VC5 VC1 VC2 VC3 VC4 VC5 VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS 42 21 Hz Fig 4 6 3 2 Drive waveform for 1 24 duty FLCKS 00B ...

Page 75: ...COM1 COM2 SEG0 SEG1 COM0 SEG0 COM0 SEG1 VDD VSS VC5 VC4 VC2 VC3 VC1 VSS VC5 VC4 VC2 VC3 VC1 VSS VC5 VC4 VC2 VC3 VC1 VSS VC5 VC4 VC2 VC3 VC1 VSS VC5 VC4 VC2 VC3 VC1 VSS VC5 VC4 VC2 VC3 VC1 VSS GND VC1 VC2 VC3 VC4 VC5 VC5 VC4 VC2 VC3 VC1 VSS GND VC1 VC2 VC3 VC4 VC5 32 Hz Fig 4 6 3 3 Drive waveform for 1 16 duty FLCKS 00B ...

Page 76: ...00H F101H F200H F201H F300H F301H SEG1 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 F002H F003H F102H F103H F202H F203H F302H F303H SEG2 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 F004H F005H F104H F105H F204H F205H F304H F305H SEG3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 ...

Page 77: ...2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 F002H F003H F102H F103H F202H F203H SEG2 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 F004H F005H F104H F105H F204H F205H SEG3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 F006H F007H F106H F107H F206H F207H SEG47 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 Memory address Data...

Page 78: ... SEG3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 F006H F007H F106H F107H F206H F207H F306H F307H Memory address Data bit Fig 4 6 4 3 Correspondence between display memory and LCD dot matrix 1 16 duty When a bit in the display memory is set to 1 the corresponding LCD pixel goes on and when it is set to 0 the pixel goes off When 1 16 duty is selec...

Page 79: ...he contrast can be adjusted to 16 levels using the LC3 LC0 register Table 4 6 5 1 LCD contrast No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 LC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 LC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Contrast Light Dark At initial reset the LC3 LC0 register is set to 0000B The software should initialize the register to...

Page 80: ...ions as a general purpose register when 1 24 or 1 32 is selected LCD display mode selection R W FF50H General LPAGE DSPC1 DSPC0 0 1 32 32 Hz LDUTY2 0 Duty 1 Prohibited 2 1 24 42 Hz 3 1 24 21 Hz LDUTY2 0 Duty 4 1 16 32 Hz 5 7 Prohibited FF51H General LDUTY2 LDUTY1 LDUTY0 R W General LDUTY2 LDUTY1 LDUTY0 0 0 0 0 1 0 General purpose register LCD drive duty selection FF03H VCHLMOD VDHLMOD General LPWR...

Page 81: ...ot implemented prohibition of read write Not implemented prohibition of read write Display data area COM8 COM15 Display data area COM8 COM15 Unused area Unused area Display data area 0 COM8 COM15 Not implemented prohibition of read write F200H F24FH F250H F25FH F260H F26FH F270H F2FFH Not implemented prohibition of read write Not implemented prohibition of read write Display data area COM16 COM23 ...

Page 82: ...n to allow VD2 to stabilize When 0 is written to VCSEL the LCD system voltage regulator is driven with VDD At initial reset this register is set to 0 Note Do not set DBON to 1 boost mode and VCSEL to 1 driving with VD2 if the supply voltage VDD exceeds 2 5 V as it may cause damage of the IC LPWR LCD system voltage regulator On Off register FF03H D0 Turns the LCD system voltage regulator on and off...

Page 83: ... mode select register FF50H D0 D1 Sets the display mode Table 4 6 6 4 Display mode DSPC1 1 1 0 0 Display mode All white mode All black mode Reverse mode Normal mode DSPC0 1 0 1 0 In normal mode the screen image written in the display RAM is output without being processed In reverse mode the screen image written in the display RAM is output in reverse video All black mode turns all the LCD pixels o...

Page 84: ...0B 16 Hz 10 666 Hz 21 333 Hz 16 Hz FLCKS 01B 21 333 Hz 14 22 Hz 28 44 Hz 21 333 Hz FLCKS 00B 32 Hz 21 333 Hz 42 666 Hz 32 Hz Frame frequency At initial reset this register is set to 000B LC3 LC0 LCD contrast adjustment register FF52H Adjusts the LCD contrast Table 4 6 6 6 LCD contrast No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 LC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 L...

Page 85: ...H F1FFH F270H F2FFH F370H F3FFH is made the operation is not guaranteed 2 When driving the LCD system voltage regulator with VD2 wait at least 1 msec for stabilization of the voltage before switching the power voltage for the LCD system voltage regulator to VD2 using VCSEL after the power supply voltage booster halver is turned on ...

Page 86: ...o the clock timer Table 4 7 2 1 Controlling clock timer operating clock RTCKE 1 0 Clock timer operating clock fOSC1 128 256 Hz Off If it is not necessary to run the clock timer stop the clock supply by setting RTCKE to 0 to reduce current consumption 4 7 3 Data reading and hold function The 8 bits timer data are allocated to the address FF41H and FF42H FF41H D0 TM0 128 Hz D1 TM1 64 Hz D2 TM2 32 Hz...

Page 87: ...rupt request 1 Hz interrupt request Bit D0 D1 D2 D3 D0 D1 D2 D3 Frequency Clock timer timing chart 128 Hz 64 Hz 32 Hz 16 Hz 8 Hz 4 Hz 2 Hz 1 Hz Fig 4 7 4 1 Timing chart of clock timer As shown in Figure 4 7 4 1 an interrupt is generated at the falling edge of each frequency signal 128 Hz 64 Hz 32 Hz 16 Hz 8 Hz 4 Hz 2 Hz 1 Hz At this time the corresponding interrupt factor flag IT0 IT1 IT2 IT3 IT4 ...

Page 88: ...Clock timer 2 Hz Interrupt mask register Clock timer 4 Hz Interrupt mask register Clock timer 8 Hz FFEEH EIT3 EIT2 EIT1 EIT0 R W EIT3 EIT2 EIT1 EIT0 0 0 0 0 Enable Enable Enable Enable Mask Mask Mask Mask FFEFH EIT7 EIT6 EIT5 EIT4 R W EIT7 EIT6 EIT5 EIT4 0 0 0 0 Enable Enable Enable Enable Mask Mask Mask Mask FFFEH IT3 IT2 IT1 IT0 R W IT3 IT2 IT1 IT0 0 0 0 0 R Yes W Reset R No W Invalid FFFFH IT7 ...

Page 89: ... Timer data FF41H FF42H The 128 1 Hz timer data of the clock timer can be read out with these registers These eight bits are read only and writing operations are invalid By reading the low order data FF41H the high order data FF42H is latched The latched value not the current value is always read as the high order data Therefore be sure to read the low order data first At initial reset the timer d...

Page 90: ... occur again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state At initial reset these flags are set to 0 4 7 6 Programming notes 1 Be sure to read timer data in the order of low ord...

Page 91: ...ffer SWD0 3 reading SWD4 7 reading SWD8 11 reading SWRST 10 Hz interrupt request Capture control circuit SWRUN EDIR CRNWF DKM2 0 LCURF Direct RUN interrupt request Direct LAP interrupt request 1 000 Hz Direct input control SWDIR P11 P10 P12 P13 P40 P43 Fig 4 8 1 1 Block diagram of stopwatch timer The stopwatch timer can be used as a separate timer from the clock timer In particular digital watch s...

Page 92: ...he prescaler output clock 1 000 Hz 100 Hz generated by SWD0 3 and 10 Hz generated by SWD4 7 are approximate values 4 8 4 Capture buffer and hold function The stopwatch data 1 1 000 sec 1 100 sec and 1 10 sec can be read from SWD0 3 FF4BH SWD4 7 FF4CH and SWD8 11 FF4DH respectively The counter data are latched in the capture buffer when reading and are held until reading of three words is completed...

Page 93: ...alling edge of the 1 024 Hz same as the prescaler input clock The SWRUN register can be read and in this case it indicates the operating status of the stopwatch timer Figure 4 8 5 1 shows the operating timing when controlling the SWRUN register fOSC1 32 1 024 Hz SWRUN writing SWRUN register Count clock Fig 4 8 5 1 Operating timing when controlling SWRUN When the direct input function explained in ...

Page 94: ... as the SW RUN control The chattering judgment is performed at the point where the key turns off and a chatter ing less than 46 8 62 5 msec is removed Therefore more time is needed for an interval between RUN and STOP key inputs Figure 4 8 6 1 shows the operating timing for the direct RUN input fOSC1 32 1 024 Hz Direct RUN input P10 P11 Direct RUN internal signal SWRUN register Count clock Direct ...

Page 95: ... P11 P10 Direct LAP internal signal Data holding Direct LAP interrupt SWD8 11 reading Fig 4 8 6 2 Operating timing for direct LAP input Direct LAP input P11 P10 Capture renewal flag CRNWF SWD0 3 reading SWD4 7 reading SWD8 11 reading Data holding 1 Hz interrupt factor flag ISW1 Lap data carry up request flag LCURF Counter data 999 000 Fig 4 8 6 3 Timing for data holding and reading during direct L...

Page 96: ...tatus 1 Either the RUN or LAP key is pressed independently if no other key is been held down 2 Both the RUN and LAP keys are pressed at the same time if no other key is held down RUN and LAP functions are effective 3 The RUN or LAP key is pressed if either is held down RUN and LAP functions are effective 4 Either the RUN or LAP key and the mask key are pressed at the same time if no other key is h...

Page 97: ... Stopwatch timer SWD0 3 timing chart FF4BH 1 1 000 sec BCD D0 D1 D2 D3 Address Register Stopwatch timer SWD4 7 timing chart Address Register Stopwatch timer SWD8 11 timing chart Fig 4 8 7 1 Timing chart for counters As shown in Figure 4 8 7 1 the interrupts are generated by the overflow of their respective counters 9 changing to 0 Also at this time the corresponding interrupt factor flag ISW10 ISW...

Page 98: ...unctions use the P10 and P11 ports Therefore the direct input interrupt and the P10 P13 inputs interrupt may generate at the same time depending on the interrupt condition setting for the input port P10 P13 Consequently when using the direct input interrupt set the inter rupt select registers SIP10 and SIP11 to 0 so that the input interrupt does not generate by P10 and P11 inputs fOSC1 32 1 024 Hz...

Page 99: ...0 SWD3 SWD2 SWD1 SWD0 0 0 0 0 Stopwatch timer data BCD 1 1000 sec 0 0 SWDIR EDIR R R W 0 3 0 3 SWDIR EDIR 2 2 0 0 Enable Disable Unused Unused Stopwatch direct input switch 0 P10 Run Stop P11 Lap 1 P10 Lap P11 Run Stop Direct input enable FFEDH EIRUN EILAP EISW1 EISW10 R W EIRUN EILAP EISW1 EISW10 0 0 0 0 Enable Enable Enable Enable Mask Mask Mask Mask Interrupt mask register Stopwatch direct RUN ...

Page 100: ...watch timer as the RUN STOP and LAP inputs according to this selection At initial reset this register is set to 0 DKM0 DKM2 Direct key mask select register FF49H D0 D2 Selects a combination of the key inputs for concurrence judgment with RUN and LAP inputs when the direct input function is set Table 4 8 8 2 Key mask selection DKM2 0 0 0 0 1 1 1 1 DKM1 0 0 1 1 0 0 1 1 DKM0 0 1 0 1 0 1 0 1 Mask key ...

Page 101: ...when the data held into the capture buffer has not yet been read Reading SWD8 11 in that status sets this flag to 1 and the hold status is maintained Consequently when data that is held by a LAP input is read read this flag after reading the SWD8 11 and check whether the data has been renewed or not This flag is renewed when SWD8 11 is read At initial reset this flag is set to 0 LCURF Lap data car...

Page 102: ...t RUN direct LAP 1 Hz and 10 Hz interrupts At initial reset these registers are set to 0 IRUN ILAP ISW1 ISW10 Interrupt factor flags FFFDH These flags indicate the status of the stopwatch timer interrupt When 1 is read Interrupt has occurred When 0 is read Interrupt has not occurred When 1 is written Flag reset When 0 is written Invalid The interrupt factor flags IRUN ILAP ISW1 and ISW10 correspon...

Page 103: ...been renewed or not 4 When performing a processing such as a LAP input preceding with 1 Hz interrupt processing read the LAP data carry up request flag LCURF before processing and check whether carry up is needed or not 5 After an interrupt occurs the same interrupt will occur again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag ...

Page 104: ...bit compare data register in addition to the above registers This register is used to store data to be compared with the contents of the down counter When the timer is set to PWM mode the timer outputs the compare match signal if the contents between the down counter and the compare data register are matched and an interrupt occurs at the same time Also the compare match signal is used with the un...

Page 105: ...form generator Data buffer PTD30 PTD37 Comparator Fig 4 9 1 2 Configuration of programmable timer Ch B Timers 2 and 3 Timer 4 Timer 4 clock selection Underflow signal Compare match signal Interrupt request Timer 4 reset Timer 4 clock Timer 5 clock PWM output selection P42 PTSEL4 PTRST4 Data bus Timer 4 Run Stop PTRUN4 PTPS40 PTPS43 Timer function setting fOSC1 16 2 048 Hz fOSC1 FCSEL_C Timer 5 clo...

Page 106: ... structure except the register names I O ports used and their signal names To simplify the explanations the subsequent sections are described using Ch A Timers 0 and 1 The register and signal names have a timer number 0 to 7 or unit Ch name A to D They are described using the names for Ch A Timers 0 and 1 or x timer number 0 to 7 except when a specific description is required Description for Ch A ...

Page 107: ... Table 4 9 2 1 Selecting count clock frequency PTPSx3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 PTPSx2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 PTPSx1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 PTPSx0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Timer clock fOSC3 fOSC3 2 fOSC3 4 fOSC3 8 fOSC3 16 fOSC3 32 fOSC3 64 fOSC3 256 fOSC1 32 kHz fOSC1 2 16 kHz fOSC1 4 8 kHz fOSC1 16 2 kHz fOSC1 32 1 kHz fOSC1 64 512 Hz fOSC1 256 128 Hz OFF fOSC1 OSC...

Page 108: ...ins its data while stopped and can restart counting continuing from that data The counter data can be read via the data buffer PTDx0 PTDx7 in optional timing However the counter has the data hold function the same as the clock timer that holds the high order data PTDx4 PTDx7 when the low order data PTDx0 PTDx3 is read in order to prevent the borrowing operation between low and high order reading t...

Page 109: ...er the falling edge is selected and when 1 is written the rising edge is selected The count down timing is shown in Figure 4 9 4 1 EVIN_A input Count data n n 1 n 2 n 3 n 4 n 5 n 6 PLPUL_A EVCNT_A 0 1 1 PTRUN0 Fig 4 9 4 1 Timing chart in event counter mode The event counter mode also allows use of a noise reject function to eliminate noise such as chattering on the external clock EVIN_A This funct...

Page 110: ...the cycle and duty ratio of the output signal can be controlled using the reload data register and the compare data register respectively to generate a PWM signal Note however the following condition must be met RLD reload data CD compare data and CD 0 If RLD CD the output signal is fixed at 1 after the first underflow occurs and does not fall to 0 The generated PWM signal can be output from an I ...

Page 111: ...1 2 Fig 4 9 6 1 Configuration of 16 bit timer Timer 0 1 In 16 bit timer mode the Timer 0 register settings are effective for timer RUN STOP control and count clock frequency selection The event counter function can also be used Timer 1 uses the Timer 0 underflow signal as the count clock therefore the Timer 1 RUN STOP control and count clock frequency select registers become invalid However the PW...

Page 112: ...generated as described above is output as the TOUT_A signal Table 4 9 8 1 TOUT outputs and control registers Output select register CHSEL_A 0 CHSEL_A 1 Output control register PTOUT_A Output clock name TOUT_A Output terminal P13 Output timer Timer 0 Timer 1 It is possible to select either Timer 0 or Timer 1 output to be used by the TOUT output channel select register CHSEL_A In 16 bit timer mode T...

Page 113: ...ary to control with the PTOUT_A register PTRUN1 Timer 1 underflow Source clock for serial I F and R f converter Fig 4 9 9 1 Clock output to serial interface and R f converter A setting value for the RLD1x register according to a transfer rate of the serial interface is calculated by the following expression fCNT1 RLD1x 1 2 bps fCNT1 Timer 1 count clock frequency set by the PTPS1 register See Table...

Page 114: ...y PTPS33 30 Frequency 0 Off 1 fOSC1 256 2 fOSC1 64 3 fOSC1 32 4 fOSC1 16 5 fOSC1 4 6 fOSC1 2 11 fOSC3 16 7 fOSC1 12 fOSC3 8 8 fOSC3 256 13 fOSC3 4 9 fOSC3 64 14 fOSC3 2 10 fOSC3 32 15 fOSC3 FF1CH PTPS43 PTPS42 PTPS41 PTPS40 R W PTPS43 PTPS42 PTPS41 PTPS40 0 0 0 0 Programmable timer 4 count clock frequency selection PTPS43 40 Frequency PTPS43 40 Frequency PTPS43 40 Frequency 0 Off 1 fOSC1 256 2 fOS...

Page 115: ...PTD01 PTD00 PTD07 PTD06 PTD05 PTD04 0 0 0 0 R FF89H PTD07 PTD06 PTD05 PTD04 CD03 CD02 CD01 CD00 0 0 0 0 R W FF8CH CD03 CD02 CD01 CD00 PTD13 PTD12 PTD11 PTD10 0 0 0 0 R FF8AH PTD13 PTD12 PTD11 PTD10 PTD17 PTD16 PTD15 PTD14 0 0 0 0 R FF8BH PTD17 PTD16 PTD15 PTD14 CD07 CD06 CD05 CD04 0 0 0 0 R W FF8DH CD07 CD06 CD05 CD04 CD13 CD12 CD11 CD10 0 0 0 0 R W FF8EH CD13 CD12 CD11 CD10 CD17 CD16 CD15 CD14 0 ...

Page 116: ...D25 CD24 0 0 0 0 R W FF9DH CD27 CD26 CD25 CD24 CD33 CD32 CD31 CD30 0 0 0 0 R W FF9EH CD33 CD32 CD31 CD30 CD37 CD36 CD35 CD34 0 0 0 0 R W FF9FH CD37 CD36 CD35 CD34 MSB Programmable timer 3 reload data low order 4 bits LSB MSB Programmable timer 3 reload data high order 4 bits LSB MSB Programmable timer 2 data low order 4 bits LSB MSB Programmable timer 2 data high order 4 bits LSB MSB Programmable ...

Page 117: ...UN4 2 0 2 0 Reset Run Reset Run Invalid Stop Invalid Stop W R W W R W FFA2H PTRST5 PTRUN5 PTRST4 PTRUN4 RLD43 RLD42 RLD41 RLD40 0 0 0 0 R W FFA4H RLD43 RLD42 RLD41 RLD40 RLD47 RLD46 RLD45 RLD44 0 0 0 0 R W FFA5H RLD47 RLD46 RLD45 RLD44 CD57 CD56 CD55 CD54 0 0 0 0 MSB Programmable timer 5 reload data low order 4 bits LSB MSB Programmable timer 5 reload data high order 4 bits LSB MSB Programmable ti...

Page 118: ...7 RLD66 RLD65 RLD64 CD73 CD72 CD71 CD70 0 0 0 0 R W FFBEH CD73 CD72 CD71 CD70 MSB Programmable timer 7 reload data low order 4 bits LSB MSB Programmable timer 7 reload data high order 4 bits LSB MSB Programmable timer 6 data low order 4 bits LSB MSB Programmable timer 6 data high order 4 bits LSB MSB Programmable timer 6 compare data low order 4 bits LSB MSB Programmable timer 7 data low order 4 b...

Page 119: ...sk register Programmable timer 4 underflow Interrupt mask register Programmable timer 4 compare match General purpose register General purpose register Interrupt mask register Programmable timer 5 underflow Interrupt mask register Programmable timer 5 compare match General purpose register General purpose register Interrupt mask register Programmable timer 6 underflow Interrupt mask register Progr...

Page 120: ...gister FF1EH PTPS70 PTPS73 Timer 7 count clock frequency select register FF1FH Selects the count clock frequency for each timer Table 4 9 10 2 Selecting count clock frequency PTPSx3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 PTPSx2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 PTPSx1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 PTPSx0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Timer clock fOSC3 fOSC3 2 fOSC3 4 fOSC3 8 fOSC3 16 fOSC3 32 fOSC3 64 ...

Page 121: ... clock input from P12 P41 P42 or P43 with 0 98 msec or more pulse width The noise rejector allows the coun ter to input the clock at the second falling edge of the internal 2 048 Hz signal after changing the input level of the I O port terminal Consequently the pulse width of noise that can reliably be rejected is 0 48 msec or less fOSC1 32 768 kHz When 0 is written to these registers the noise re...

Page 122: ...ely using each PTRSTx register These operations are the same when Timers 2 and 3 Timers 4 and 5 or Timers 6 and 7 are used as a 16 bit timer At initial reset these registers are set to 0 PTOUT_A TOUT_A output control register FF81H D0 Controls TOUT signal outputs When 1 is written TOUT output On When 0 is written TOUT output Off Reading Valid When 1 is written to the register the corresponding TOU...

Page 123: ...D2 PTRUN6 Timer 6 RUN STOP control register FFB2H D0 PTRUN7 Timer 7 RUN STOP control register FFB2H D2 Controls the RUN STOP of the counter When 1 is written RUN When 0 is written STOP Reading Valid The counter in Timer x starts counting down by writing 1 to the PTRUNx register and stops by writing 0 In STOP status the counter data is maintained until the counter is reset or is set in the next RUN...

Page 124: ...er data FFA8H FFA9H PTD50 PTD57 Timer 5 counter data FFAAH FFABH PTD60 PTD67 Timer 6 counter data FFB8H FFB9H PTD70 PTD77 Timer 7 counter data FFBAH FFBBH Count data in the programmable timer can be read from these latches The low order 4 bits of the count data in Timer x can be read from PTDx0 PTDx3 and the high order data can be read from PTDx4 PTDx7 Since the high order 4 bits are held by readi...

Page 125: ...Timer 5 interrupt factor flags FFF7H D1 D0 IPT6 ICTC6 Timer 6 interrupt factor flags FFF8H D1 D0 IPT7 ICTC7 Timer 7 interrupt factor flags FFF9H D1 D0 These flags indicate the status of the programmable timer interrupt When 1 is read Interrupt has occurred When 0 is read Interrupt has not occurred When 1 is written Flag reset When 0 is written Invalid IPTx and ICTCx are the interrupt factor flags ...

Page 126: ...nt counter mode the timer starts counting at the first event clock 42H 41H 40H 3FH 3EH 3DH 1 RUN writing 0 STOP writing PTRUNx WR PTDx0 PTDx7 PTRUNx RD Count clock Fig 4 9 11 2 Timing chart for RUN STOP control event counter mode 3 Since the TOUT_A signal is generated asynchronously from the PTOUT_A register a hazard within 1 2 cycle is generated when the signal is turned on and off by setting the...

Page 127: ...nderflow interrupt is generated Fig 4 9 11 3 Reload timing for programmable timer To avoid improper reloading do not rewrite the reload data after an interrupt occurs until the counter data is determined including the reloading period Be especially careful when using the OSC1 low speed clock as the clock source of the programmable timer and the CPU is operating with the OSC3 high speed clock 7 The...

Page 128: ...ig 4 10 1 1 Configuration of serial interface 4 10 2 Serial interface terminals The following shows the terminals used in the serial interface and their functions SCLK P20 Inputs or outputs the serial clock By writing 1 to the ESIF register to enable the serial interface the P20 terminal is switched to the SCLK terminal In master mode the SCLK terminal is configured for output and it outputs the s...

Page 129: ...the I O port is also applied to the serial interface terminals Output specification The output specification of the SOUT SCLK in master mode and SRDY in slave mode terminals that are used as the serial interface outputs is respectively selected by the mask options for P21 P20 and P23 Either complementary output or P channel open drain output can be selected as the output specifica tion However whe...

Page 130: ...aster device to control data transfer the serial interface can output a ready signal indicating that it is ready to transfer from the SRDY terminal by hardware control SPI slave mode SPI slave mode is provided to use the S1C63616 as an SPI slave device In this mode the serial interface inputs the synchronous clock that is sent by the external master device from the SCLK terminal to per form serial...

Page 131: ...ble 4 10 5 1 Table 4 10 5 1 Serial interface clock frequencies SIFCKS2 1 1 1 1 0 0 0 0 SIFCKS1 1 1 0 0 1 1 0 0 SIFCKS0 1 0 1 0 1 0 1 0 SIF clock master mode fOSC3 4 fOSC3 2 fOSC3 1 Programmable timer 1 fOSC1 4 8 kHz fOSC1 2 16 kHz fOSC1 1 32 kHz Off slave mode fOSC1 OSC1 oscillation frequency indicates the frequency when fOSC1 32 kHz fOSC3 OSC3 oscillation frequency The maximum clock frequency is ...

Page 132: ...output from to the SCLK P20 terminal The data in the shift register is shifted at the falling edge of the SCLK signal when the SCPS0 register is 0 or at the rising edge of the SCLK signal when the SCPS0 register is 1 When the output of the 8 bit data from SD0 to SD7 is completed the interrupt factor flag ISIF is set to 1 and an interrupt occurs Moreover the interrupt can be masked by the interrupt...

Page 133: ...e mode write 1 to the ENCS and ESREADY registers this signal cannot be used in SPI slave mode Output timing of SRDY signal is as follows When positive polarity SCPS1 0 is selected for the synchronous clock The SRDY signal goes 1 high when the S1C63616 serial interface is ready to transmit or receive data normally it is at 0 low The SRDY signal changes from 0 to 1 immediately after 1 is written to ...

Page 134: ...ISIF SRDY Slave mode a When SCPS1 0 and SCPS0 0 b When SCPS1 0 SCPS0 1 c When SCPS1 1 SCPS0 0 d When SCPS1 1 SCPS0 1 SCTRG W SCTRG R SCLK SIN 8 bit shift register SOUT ISIF SRDY Slave mode SCTRG W SCTRG R SCLK SIN 8 bit shift register SOUT ISIF SRDY Slave mode SCTRG W SCTRG R SCLK SIN 8 bit shift register SOUT ISIF SRDY Slave mode Fig 4 10 6 2 Serial interface timing chart ...

Page 135: ...rface does not start data transfer even if the synchronous clock is input to the SCLK terminal SPI master device When using the S1C63616 as an SPI master device set the serial interface to master mode ESIF 1 SMOD 1 ENCS 0 ESREADY 0 ESOUT 1 when SOUT is used The SS signal output terminal is not available in master mode set an I O port to output mode and use it as the SS signal output terminal The S...

Page 136: ...ce level select register SCLK I input I F level select register when SIF slave is used functions as a general purpose register when SIF master is used SMT23 SMT22 SMT21 SMT20 1 1 1 1 Schmitt Schmitt Schmitt Schmitt CMOS CMOS CMOS CMOS SMT23 SMT22 SMT21 SMT20 FF58H 0 ESOUT SCTRG ESIF R R W 0 3 ESOUT SCTRG ESIF 2 0 0 0 Enable Trigger Run SIF Disable Invalid Stop I O Unused SOUT enable Serial I F clo...

Page 137: ...he pull down of the SIN SCLK in slave mode and S _____ S in SPI slave mode terminals When 1 is written Pull down On When 0 is written Pull down Off Reading Valid Enables or disables the pull down resistors built into the SIN P22 SCLK P20 and S _____ S P23 terminals Pull down resistor is only built in the port selected by mask option The SCLK and SS pull down resistors are effective only in slave m...

Page 138: ...tting the trigger Supply trigger only once every time the serial interface is placed in the RUN state Refrain from performing trigger input multiple times as leads to malfunctioning Moreover when the synchronous clock SCLK is external clock start to input the external clock after the trigger When reading When 1 is read RUN during input output the synchronous clock When 0 is read STOP the synchrono...

Page 139: ...n the SCPS0 register is 0 or at the falling edge of the SCLK signal when the SCPS0 register is 1 The shift register is sequentially shifted as the data is fetched During transmitting the serial data output to the SOUT P21 terminal changes at the rising edge of the clock input or output from to the SCLK P20 terminal The data in the shift register is shifted at the rising edge of the SCLK signal whe...

Page 140: ...erted into serial data and output from the SOUT P21 terminal data bits set at 1 are output as high VDD level and data bits set at 0 are output as low VSS level When reading When 1 is read High level When 0 is read Low level The serial data input from the SIN P22 terminal can be read from these registers The serial data input from the SIN P22 terminal is converted into parallel data as a high VDD l...

Page 141: ...igger condition it is required that data writing or reading on data registers SD0 SD7 be per formed prior to writing 1 to SCTRG The internal circuit of the serial interface is initiated through data writing reading on data registers SD0 SD7 In addition be sure to enable the serial interface with the ESIF register before setting the trigger Supply trigger only once every time the serial interface i...

Page 142: ...nent does not affect the IC power supply Refer to Output Terminals in Section 5 3 Precautions on Mounting for more information 4 11 2 Controlling clock manager To generate the buzzer signal the clock for the sound generator must be supplied from the clock manager by writing 1 to the SGCKE register in advance Table 4 11 2 1 Controlling sound generator clock SGCKE 1 0 Sound generator clock Programma...

Page 143: ...evel 2 Level 3 Level 4 Level 5 Level 6 Level 7 Level 8 Min 4096 0 2048 0 8 16 7 16 6 16 5 16 4 16 3 16 2 16 1 16 3276 8 1638 4 8 20 7 20 6 20 5 20 4 20 3 20 2 20 1 20 2730 7 1365 3 12 24 11 24 10 24 9 24 8 24 7 24 6 24 5 24 2340 6 1170 3 12 28 11 28 10 28 9 28 8 28 7 28 6 28 5 28 Duty ratio by buzzer frequency Hz When the high level output time has been made TH and when the low level output time h...

Page 144: ...it is retained at that level The duty ratio can be returned to maximum by writing 1 into register ENRST during output of a envelope attached buzzer signal The envelope attenuation time time for changing of the duty ratio can be selected by the register ENRTM The time for a 1 stage level change is 62 5 msec 16 Hz when 0 has been written into ENRTM and 125 msec 8 Hz when to 1 has been written Howeve...

Page 145: ...SHT is 1 the one shot output circuit is in operation during one shot output and when it is 0 it shows that the circuit is in the ready outputtable status In addition it can also terminate one shot output prior to the elapsing of the set time This is done by writing a 1 into the one shot buzzer stop BZSTP In this case as well the buzzer signal goes off in synchronization with the 256 Hz signal When...

Page 146: ... FF45H 0 BZSTP BZSHT SHTPW R W R W 0 3 BZSTP 3 BZSHT SHTPW 2 0 0 0 Stop Trigger Busy 125 msec Invalid Invalid Ready 31 25 msec Unused 1 shot buzzer stop writing 1 shot buzzer trigger writing 1 shot buzzer status reading 1 shot buzzer pulse width setting 1 Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read SGCKE Sound generator clock enable register FF16H D2 Cont...

Page 147: ...gital envelope is determined by the time for converting the duty ratio When 1 is written to ENRTM it becomes 125 msec 8 Hz units and when 0 is written it becomes 62 5 msec 16 Hz units At initial reset this register is set to 0 SHTPW One shot buzzer pulse width setting register FF45H D0 Selects the output time of the one shot buzzer When 1 is written 125 msec When 0 is written 31 25 msec Reading Va...

Page 148: ...zer frequency Hz 4096 0 3276 8 2730 7 2340 6 2048 0 1638 4 1365 3 1170 3 BZFQ0 0 1 0 1 0 1 0 1 BZFQ1 0 0 1 1 0 0 1 1 BZFQ2 0 0 0 0 1 1 1 1 Select the buzzer frequency from among the above 8 types that have divided the oscillation clock At initial reset this register is set to 0 BDTY0 BDTY2 Duty level select register FF47H D0 D2 Selects the duty ratio of the buzzer signal as shown in Table 4 11 7 3...

Page 149: ...al that is out of synchronization with the BZE register hazards may at times be produced when the signal goes on off due to the setting of the BZE register 2 The one shot output is only valid when the normal buzzer output is off BZE 0 and will be invalid when the normal buzzer output is on BZE 1 ...

Page 150: ...clock MDCKE 1 0 Integer multiplier clock When CLKCHG 0 fOSC1 32 kHz When OSCC 1 CLKCHG 1 fOSC3 Off If it is not necessary to run the integer multiplier stop the clock supply by setting MDCKE to 0 to reduce current consumption 4 12 3 Multiplication mode To perform a multiplication set the multiplier to the source register SR and the multiplicand to the low order 8 bits DRL of the destination regist...

Page 151: ... in DRL is 00H and reset when it is not 00H Examples of division DRH DRL dividend SR divisor DRL quotient DRH remainder NF VF ZF 1A16H 64H 42H 4EH 0 0 0 332CH 64H 83H 00H 1 0 0 0000H 58H 00H 00H 0 0 1 2468H 13H 68H 24H 1 1 0 In the example of 2468H 13H shown above DRH DRL maintains the dividend because the quotient overflows the 8 bit To get the correct results when an overflow has occurred perfor...

Page 152: ...rc_data h ldb xl src_data l Set RAM address for operand ldb ext au h ldb yl au l Set multiplier I O memory address ldb ba x ldb y ba Set data to SR ldb ba x ldb y ba Set data to DRL ldb ba x ldb y ba Set data to DRH ld y 0b0001 Start operation select calculation mode ldb ext rslt_data h ldb xl rslt_data l Set result store address nop nop nop Dummy instructions to wait end of operation bit y 0b0100...

Page 153: ...r 4 bits LSB MSB Source register high order 4 bits FF16H MDCKE SGCKE SWCKE RTCKE R W MDCKE SGCKE SWCKE RTCKE 0 0 0 0 Enable Enable Enable Enable Disable Disable Disable Disable Integer multiplier clock enable Sound generator clock enable Stopwatch timer clock enable Clock timer clock enable 1 Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read MDCKE Integer multi...

Page 154: ...hen an operation starts by writing 1 to FF76H D0 and then a division is performed in 10 CPU clock cycles 5 bus cycles After the operation has finished the remainder is loaded to this register However if an overflow occurs in a division process the remainder is not loaded and the high order 8 bits of the dividend remains At initial reset this register is undefined CALMD Calculation mode select regi...

Page 155: ...Invalid NF is a read only bit so writing operation is invalid At initial reset this flag is set to 0 4 12 7 Programming note An operation process takes 10 CPU clock cycles 5 bus cycles after writing to the calculation mode select register CALMD until the operation result is set to the destination register DRH DRL and the operation flags While this operation is in process do not read write from to ...

Page 156: ...erted into frequency by the CR oscillation circuit and the number of clocks is counted in the built in measurement counter By reading the value of the measurement counter it can obtain the data after digitally converting the value detected by the sensor Various sensor circuits such as temperature humidity measurement circuits can be easily realized using this R f converter The configuration of the...

Page 157: ...re operat ing the serial interface Refer to Section 4 9 Programmable Timer for controlling the programmable timer If it is not necessary to run the R f converter stop the clock supply by setting RFCKS0 RFCKS2 to 000B to reduce current consumption 4 13 3 Connection terminals and CR oscillation circuit The R f converter channel 0 input output terminals and the RFOUT output terminal are shared with t...

Page 158: ...thod by setting ERFx to 11B This method should be selected for R f conversion using a normal resistive sensor DC bias such as temperature measurement using a thermistor At initial reset channel 1 is set into this conversion method Figure 4 13 3 1 shows the connection diagram of external elements RSEN RREF VSS CRFC RSEN RREF Open CRFC SEN0 P02 REF0 P01 RFIN0 P00 Channel 0 VSS SEN1 HUD REF1 RFIN1 Ch...

Page 159: ...r overflows counter 00000H By resetting the time base counter to 00000H before starting an R f conversion for the reference resistance the reference oscillation time will be obtained from the time base counter Then start an R f conversion for the sensor the measurement counter starts counting up from 00000H and the time base counter starts counting up from the counted value The counters stop count...

Page 160: ...ation timing chart An R f conversion for the sensor starts by writing 1 to the RFRUNS register When performing this sensor oscillation after an reference oscillation has completed it is not necessary to set initial values to the counters If converting the sensor resistance independently the measurement counter must be set to 00000H and the time base counter must be set to the value measured at the...

Page 161: ...eference oscillation 1 Set the initial value 00000H x 2 Start sensor oscillation Set RFRUNS to 1 Sensor oscillation Fig 4 13 4 3 Sequence of R f conversion Note Set the initial value of the measurement counter taking into account the measurable range and the overflow of counters 4 13 5 Interrupt function The R f converter has a function which allows interrupt to occur when an R f conversion has co...

Page 162: ...on interrupt 0 x x 4 x 5 1 2 3 FFFFDH FFFFEH FFFFFH 0 y 2 y 1 y x 1 x 2 Oscillation by sensor resistance R f converter clock RFRUNS register Time base counter Measurement counter clock Measurement counter IRFE OVMC Interrupt request Count up x 3 Overflow Fig 4 13 5 3 Error interrupt due to measurement counter overflow n 0 FFFFCH FFFFBH n 1 n 2 n 3 m 2 m 1 m π0 Undefined 3 2 1 0 FFFFFH FFFFEH Oscil...

Page 163: ...ERF1 ERF0 R W RFCNT RFOUT ERF1 ERF0 0 0 0 0 Continue Enable Normal Disable Continuous oscillation enable RFOUT enable R f conversion selection 0 I O 1 Ch 0 DC 2 Ch 1 AC 3 Ch 1 DC ERF1 0 R f conversion MC19 MC18 MC17 MC16 2 2 2 2 MSB Measurement counter MC16 MC19 R W FF66H MC19 MC18 MC17 MC16 R W MC11 MC10 MC9 MC8 2 2 2 2 Measurement counter MC8 MC11 FF64H MC11 MC10 MC9 MC8 R W MC15 MC14 MC13 MC12 ...

Page 164: ... R f converter clock fOSC3 4 fOSC3 2 fOSC3 1 Programmable timer 1 fOSC1 4 8 kHz fOSC1 2 16 kHz fOSC1 1 32 kHz Off fOSC1 OSC1 oscillation frequency indicates the frequency when fOSC1 32 kHz fOSC3 OSC3 oscillation frequency When programmable timer 1 is selected the programmable timer 1 underflow signal is divided by 2 before it is used as the R f converter clock In this case the programmable timer m...

Page 165: ...held at 1 while the R f conversion is being processed and is set to 0 when the R f conversion has completed Writing 0 during an R f conversion stops the CR oscillation When the channel 1 sensor type AC bias and DC bias is changed by ERF0 ERF1 during sensor oscillation RFRUNS is not reset In this case reset RFRUNS by writing 0 If RFRUNS and RFRUNR are set to 1 simultaneously RFRUNR is effective At ...

Page 166: ...y after a reference oscillation has completed The sensor oscillation and measurement counter stop when the time base counter overflows Number of clocks counted by the sensor oscillation can be evaluated from the value indicated by the counter when it stops Calculate the target value by processing the above counted number according to the program Measurable range and the overflow of the counter mus...

Page 167: ...r again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state After an initial reset these flags are set to 0 4 13 8 Programming notes 1 When an error interrupt occurs reset the overflo...

Page 168: ...ns of software whether the supply voltage is normal or has dropped The criteria voltage can be selected from 16 types shown in Table 4 14 2 1 using the SVDS3 SVDS0 register Table 4 14 2 1 Criteria voltage SVDS3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 SVDS2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 SVDS1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 SVDS0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Criteria voltage V 3 2 3 1 3 0 2 9 2 8 2 7 ...

Page 169: ...urns the SVD circuit on and off When 1 is written SVD circuit On When 0 is written SVD circuit Off Reading Valid When SVDON is set to 1 a source voltage detection is executed by the SVD circuit As soon as SVDON is reset to 0 the result is loaded to the SVDDT latch To obtain a stable detection result the SVD circuit must be on for at least 500 µsec At initial reset this register is set to 0 SVDDT S...

Page 170: ...SLEEP functions that considerably reduce current consumption when it is not necessary The CPU enters HALT status when the HALT instruction is executed In HALT status the operation of the CPU is stopped However timers continue counting since the oscillation circuit operates Reactivating the CPU from HALT status is done by generating a hardware interrupt request including NMI When the CPU enters SLE...

Page 171: ...y select register 1 interrupt request signal is generated at the falling edge 8 2 Confirm the input to the P1 4 x port is surely LOW level when the P1 4 x port interrupt polarity select register 0 interrupt request signal is generated at the rising edge 9 Execute SLP instruction When SLEEP status is canceled by an I O port interrupt wait for oscillation to stabilize then restart the CPU operation ...

Page 172: ...EICTC2 IPT3 EIPT3 ICTC3 EICTC3 IPT4 EIPT4 ICTC4 EICTC4 IPT5 EIPT5 ICTC5 EICTC5 IPT6 EIPT6 ICTC6 EICTC6 IPT7 EIPT7 ICTC7 EICTC7 ISIF EISIF PCP03 SIP03 IK03 EIK03 IRFS EIRFS P13 PCP02 SIP02 IK02 EIK02 P12 PCP01 SIP01 IK01 EIK01 P11 PCP00 SIP00 IK00 EIK00 P10 SLEEP cancellation PCP13 SIP13 IK13 EIK13 P43 PCP12 SIP12 IK12 EIK12 P42 PCP11 SIP11 IK11 EIK11 P41 PCP10 SIP10 IK10 EIK10 P40 IT3 EIT3 IT2 EIT...

Page 173: ...r 7 compare match Serial interface 8 bit data input output completion Key input interrupt P13 Key input interrupt P12 Key input interrupt P11 Key input interrupt P10 Key input interrupt P43 Key input interrupt P42 Key input interrupt P41 Key input interrupt P40 Stopwatch timer Direct RUN Stopwatch timer Direct LAP Stopwatch timer 1 Hz Stopwatch timer 10 Hz Clock timer 16 Hz falling edge Clock time...

Page 174: ...2H D1 FFF2H D0 FFF3H D1 FFF3H D0 FFF4H D1 FFF4H D0 FFF5H D1 FFF5H D0 FFF6H D1 FFF6H D0 FFF7H D1 FFF7H D0 FFF8H D1 FFF8H D0 FFF9H D1 FFF9H D0 FFFAH D0 FFFBH D3 FFFBH D2 FFFBH D1 FFFBH D0 FFFCH D3 FFFCH D2 FFFCH D1 FFFCH D0 FFFDH D3 FFFDH D2 FFFDH D1 FFFDH D0 FFFEH D3 FFFEH D2 FFFEH D1 FFFEH D0 FFFFH D3 FFFFH D2 FFFFH D1 FFFFH D0 Interrupt factor flag EIRFE EIRFR EIRFS EIPT0 EICTC0 EIPT1 EICTC1 EIPT...

Page 175: ...imer 7 Serial interface Key input interrupt P1 Key input interrupt P4 Stopwatch timer Clock timer 128 Hz 64 Hz 32 Hz 16 Hz Clock timer 8 Hz 4 Hz 2 Hz 1 Hz Priority High Low The four low order bits of the program counter are indirectly addressed through the interrupt request Note The interrupt handler routine must be located within the range from Interrupt vector address 100H 10FH 7FH to 80H If it ...

Page 176: ...6 Rev 1 0 NO P169 3240 0412 subinterrupt vector area org 0x120 INT_RFC CALR INTRFC call Interrupt RFC RETI INT_DUMMY RETI Interrupt RFC org 0x800 INTRFC LDB yl P5CTL0 l LDB xl ITC_RFC1 l LD y x Port Output RET ...

Page 177: ...ICTC7 0 0 0 0 1 1 Enable Enable 0 0 Mask Mask FFEAH General General General EISIF R W General General General EISIF 0 0 0 0 1 1 1 Enable 0 0 0 Mask General purpose register Interrupt mask register R f converter error Interrupt mask register R f converter reference oscillate completion Interrupt mask register R f converter sensor oscillate completion General purpose register General purpose registe...

Page 178: ...ed Interrupt factor flag Programmable timer 1 underflow Interrupt factor flag Programmable timer 1 compare match Unused Unused Interrupt factor flag Programmable timer 2 underflow Interrupt factor flag Programmable timer 2 compare match Unused Unused Interrupt factor flag Programmable timer 3 underflow Interrupt factor flag Programmable timer 3 compare match Unused Unused Interrupt factor flag Pro...

Page 179: ...ag Clock timer 64 Hz Interrupt factor flag Clock timer 128 Hz Interrupt factor flag Clock timer 1 Hz Interrupt factor flag Clock timer 2 Hz Interrupt factor flag Clock timer 4 Hz Interrupt factor flag Clock timer 8 Hz R 1 Initial value at initial reset 3 Constantly 0 when being read 2 Not set in the circuit SIP03 SIP00 SIP13 SIP10 Interrupt select registers FF3CH FF3EH PCP03 PCP00 PCP13 PCP10 Inte...

Page 180: ...sing the SLEEP function set and confirm the P1 4 x input level the flag and the registers for the P1 4 x port the CPU clock and the power control according to the following procedures to be used to enter cancel SLEEP status before executing the SLP instruction surely 1 LCD system voltage regulator power source switch register VCSEL 0 Power supply voltage booster halver boost mode On Off register D...

Page 181: ... CPU CPU operating frequency Power supply voltage booster halver LCD system voltage regulator SVD circuit Control register HALT and SLP instructions CLKCHG OSCC DBON HLON LPWR SVDON Refer to Chapter 7 Electrical Characteristics for current consumption Below are the circuit statuses at initial reset CPU Operating status CPU operating frequency Low speed side CLKCHG 0 OSC3 oscillation circuit is in ...

Page 182: ...done as a pair Power control 1 When the power supply voltage booster halver is turned on the VD2 output voltage requires about 1 msec to stabilize Do not switch the power source for the voltage regulator LCD system voltage regula tor to VD2 until the stabilization time has elapsed 2 HLON is prohibited from use as it may cause malfunctions Always be sure to set to 0 3 Do not set DBON to 1 boost mod...

Page 183: ... the OSC3 oscillation circuit before output Refer to Section 4 4 Oscillation Circuit for the control and notes 6 Before the port function is configured the circuit that uses the port e g input interrupt multiple key entry reset serial interface event counter input direct RUN LAP input for stopwatch must be dis abled LCD driver 1 When a program that access no memory implemented area F070H F0FFH F17...

Page 184: ... chart for RUN STOP control event counter mode 3 Since the TOUT_A signal is generated asynchronously from the PTOUT_A register a hazard within 1 2 cycle is generated when the signal is turned on and off by setting the register 4 When the OSC3 oscillation clock is selected for the clock source it is necessary to turn the OSC3 oscilla tion ON prior to using the programmable timer However the OSC3 os...

Page 185: ...SDP register should be done before setting data to SD0 SD7 4 Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when the pro grammable timer is used as the clock source or the serial interface is used in slave mode Sound generator 1 Since it generates a buzzer signal that is out of synchronization with the BZE register hazards may at times be produced when the s...

Page 186: ...d confirm the P1 4 x input level the flag and the registers for the P1 4 x port the CPU clock and the power control according to the following procedures to be used to enter cancel SLEEP status before executing the SLP instruction surely 1 LCD system voltage regulator power source switch register VCSEL 0 Power supply voltage booster halver boost mode On Off register DBON 0 LCD system voltage regul...

Page 187: ...t tern Reset Circuit The power on reset signal which is input to the RESET terminal changes depending on conditions power rise time components used board pattern etc Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product When using the built in pull down resistor of the RESET terminal take into consid eration dispersion of the res...

Page 188: ...display To prevent this separate the traces on the printed circuit board Put one between the power supply and the IC s VDD and VSS terminals and another between the power supply and the external component that consumes the large amount of current Furthermore use an external component with as low a current consumption as possible VDD VSS Piezo BZ CP Example Buzzer output circuit Precautions for Vis...

Page 189: ...n capacitor Resistor for CR oscillation Capacitor between VSS and VD1 Capacitor between VSS and VC1 Recommended value 32 768 kHz 0 25 pF 0 3 4 2 MHz 15 pF Crystal oscillation 30 pF Ceramic oscillation 15 pF Crystal oscillation 30 pF Ceramic oscillation 30 kΩ 0 1 µF 0 1 µF Symbol C3 C4 C5 C6 C7 C9 C10 C11 C12 CP Cres Name Capacitor between VSS and VC2 Capacitor between VSS and VC3 Capacitor between...

Page 190: ...Operating frequency Capacitor between VD1 and VSS Capacitor between VC1 and VSS Capacitor between VC2 and VSS Capacitor between VC3 and VSS Capacitor between VC4 and VSS Capacitor between VC5 and VSS Capacitor between CA and CB Capacitor between CA and CC Capacitor between CD and CE Capacitor between VD2 and VSS Capacitor between CF and CG Capacitor between VOSC and VSS Ta 45 to 85 C Symbol VDD fO...

Page 191: ... SEGxx COMxx Item High level input voltage Low level input voltage High level Schmitt input voltage 1 Low level Schmitt input voltage 1 High level Schmitt input voltage 2 Low level Schmitt input voltage 2 High level output current Low level output current Input leak current Output leak current Input pull down resistance Input terminal capacitance Segment Common output current 1 2 Unless otherwise ...

Page 192: ...tern is displayed No panel load A 1 MΩ load resistor is connected between VSS VC1 VSS VC2 VSS VC3 VSS VC4 and VSS VC5 The voltage booster is used when VDD 1 6 2 5V LCD drive voltage 1 4 bias VC2 reference Item LCD drive voltage Symbol VC1 VC2 VC4 VC5 Unit V V V V Max 0 265VC5 0 532VC5 0 795VC5 Typ 1 06 Typ 3 60 3 68 3 76 3 84 3 92 4 00 4 08 4 16 4 24 4 32 4 40 4 48 4 56 4 64 4 72 4 80 Min 0 235VC5...

Page 193: ...0 3 9H SVDS0 3 AH SVDS0 3 BH SVDS0 3 CH SVDS0 3 DH SVDS0 3 EH SVDS0 3 FH R F converter circuit Item Symbol Unit Max Typ Min Condition Unless otherwise specified VDD 1 6 to 5 5V VSS 0V Ta 25 C Reference sensor oscillation frequencies 1 Reference sensor oscillation frequency IC deviation 2 Reference sensor resistance 3 Reference capacitor and capacitive sensor capacitance 3 Time base counter clock f...

Page 194: ... fOSC1 32 768kHz VDD 2 5 to 5 5V 1 LCDCx All on LCx FH fOSC1 32 768kHz VDD 2 5 to 5 5V HLMOD 1 2 LCDCx All on LCx FH fOSC1 32 768kHz DBON 1 VDD 1 6 to 2 5V 3 LCDCx All on LCx FH fOSC1 32 768kHz DBON 1 VDD 1 6 to 2 5V HLMOD 1 4 LCDCx All on LCx FH fOSC1 32 768kHz VDD 2 5 to 5 5V 1 LCDCx All on LCx FH fOSC1 32 768kHz VDD 2 5 to 5 5V HLMOD 1 2 LCDCx All on LCx FH fOSC1 32 768kHz DBON 1 VDD 1 6 to 2 5...

Page 195: ...V f CG Unit s pF pF ppm ppm V ppm Condition Including the board capacitance Chip VDD constant VDD constant CG 0 to 25pF Unless otherwise specified VDD 1 6 to 5 5V VSS 0V Crystal oscillator C 002RX R1 30kΩ Typ CL 12 5pF Ta 25 C Max 3 25 10 1 Typ 14 Min 0 10 25 OSC3 ceramic oscillation circuit Item Oscillation start time Symbol tsta Unit ms Max 1 Typ Min Condition Unless otherwise specified VDD 1 6 ...

Page 196: ... VSS 0V Ta 45 to 85 C VIH1 0 8VDD VIL1 0 2VDD VOH 0 8VDD VOL 0 2VDD Slave mode Item Transmitting data output delay time Receiving data input set up time Receiving data input hold time Symbol tssd tsss tssh Unit ns ns ns Max 500 Typ Min 400 200 Note that the maximum clock frequency is limited to 1 MHz Condition VDD 3 0V VSS 0V Ta 45 to 85 C VIH1 0 8VDD VIL1 0 2VDD VOH 0 8VDD VOL 0 2VDD Master mode ...

Page 197: ...SIC63616 Rev 1 0 NO P189 3240 0412 7 7 Timing Chart System clock switching OSCC CLKCHG 10 msec min 1 instruction execution time or longer ...

Page 198: ...urrent voltage characteristic Ta 85 C Max value 0 0 0 2 4 6 8 10 12 14 0 1 0 2 0 3 0 4 0 5 0 6 VDD VOH V VDD 1 6 V VDD 3 0 V VDD 5 5 V I OH mA Low level output current voltage characteristic Ta 85 C Min value 0 0 14 12 10 8 6 4 2 0 0 1 0 2 0 3 0 4 0 5 0 6 VOL V VDD 1 6 V I OL mA VDD 3 0 V VDD 5 5 V ...

Page 199: ...ter halver not used Ta 25 C Typ value 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 7 0 6 0 5 0 4 0 3 0 2 0 VDD V V C5 V LCx FH LCx 0H LCD drive voltage supply voltage characteristic 1 5 bias VC2 reference power supply voltage booster halver used Ta 25 C Typ value 1 5 1 8 2 1 2 4 2 7 3 0 7 0 6 0 5 0 4 0 3 0 2 0 VDD V LCx FH LCx 0H V C5 V ...

Page 200: ...0 LCx FH LCx 0H LCD drive voltage supply voltage characteristic 1 4 bias VC2 reference power supply voltage booster halver used Ta 25 C Typ value 1 5 1 8 2 1 2 4 2 7 3 0 7 0 6 0 5 0 4 0 3 0 2 0 VDD V LCx FH LCx 0H V C5 V LCD drive voltage supply voltage characteristic 1 4 bias VC1 reference power supply voltage booster halver not used Ta 25 C Typ value 1 5 6 0 5 0 4 0 3 0 2 0 VDD V V C5 V 2 0 2 5 ...

Page 201: ...mperature characteristic 1 4 bias VC2 reference power supply voltage booster halver not used VDD 3 0 V Typ value 50 1 05VC5 1 04VC5 1 03VC5 1 02VC5 1 01VC5 1 00VC5 0 99VC5 0 98VC5 0 97VC5 0 96VC5 0 95VC5 0 94VC5 25 0 25 50 75 100 Ta C V C5 V LCD drive voltage ambient temperature characteristic 1 4 bias VC1 reference power supply voltage booster halver not used VDD 3 0 V Typ value 50 1 06VC5 1 05VC...

Page 202: ... V LCD drive voltage load characteristic 1 4 bias VC2 reference power supply voltage booster halver not used When a load is connected to VC5 terminal only LCx FH Ta 25 C Typ value 0 5 00 4 90 4 80 4 70 4 60 4 50 4 40 4 8 12 16 20 IVC5 µA V C5 V LCD drive voltage load characteristic 1 4 bias VC1 reference power supply voltage booster halver not used When a load is connected to VC5 terminal only LCx...

Page 203: ... NO P195 3240 0412 SVD voltage ambient temperature characteristic SVDSx FH Typ value 50 1 05VSVD 1 04VSVD 1 03VSVD 1 02VSVD 1 01VSVD 1 00VSVD 0 99VSVD 0 98VSVD 0 97VSVD 0 96VSVD 0 95VSVD 25 0 25 50 75 100 Ta C V SVD V ...

Page 204: ...lation fOSC1 32 768 kHz VDD 5 5 V OSC3 OFF Clock manager OFF Typ value 50 5 4 3 2 1 0 25 0 25 50 75 100 Ta C I HALT1 µA RUN state current consumption temperature characteristic During operation with OSC1 Crystal oscillation fOSC1 32 768 kHz VDD 5 5 V OSC3 OFF Clock manager OFF Typ value 50 5 4 3 2 1 0 25 0 25 50 75 100 Ta C I EXE1 µA ...

Page 205: ...amic oscillation VDD 5 5 V Ta 25 C Typ value 0 5 0 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 500 400 300 200 100 0 OSC3 frequency MHz I EXE2 µA RUN state current consumption resistor characteristic During operation with OSC3 CR oscillation VDD 5 5 V Ta 25 C Typ value 10 800 700 600 500 400 300 200 100 0 100 1000 RCR3 kΩ I EXE3 µA ...

Page 206: ...sistor characteristic OSC3 CR oscillation VDD 5 5 V Ta 25 C Typ value 10 10000 1000 100 10 100 1000 RCR3 kΩ f OSC3 kHz Oscillation frequency temperature characteristic OSC3 CR oscillation RCR3 30 kΩ Typ value 50 10000 1000 100 25 25 50 0 75 100 Ta C f OSC3 kHz ...

Page 207: ... C Typ value 0 1 10 100 1 000 10 000 10 000 1 000 100 10 1 0 RREF RSEN kΩ f RFCLK kHz VDD 5 5 V VDD 1 6 V IC deviation RFC reference sensor oscillation frequency resistance characteristic AC oscillation mode CSEN 1000 pF Ta 25 C Typ value 0 1 10 100 1 000 10 000 10 000 1 000 100 10 1 0 RREF RSEN kΩ f RFCLK kHz VDD 5 5 V VDD 1 6 V IC deviation ...

Page 208: ...N 100 kΩ Ta 25 C Typ value 10 100 1 000 10 000 1 000 100 10 1 0 CRFC pF f RFCLK kHz VDD 5 5 V VDD 1 6 V IC deviation RFC reference sensor oscillation frequency current consumption characteristic DC AC oscillation mode CRFC 1000 pF Ta 25 C Typ value 0 1 10 100 1 000 10 000 fRFC kHz I RFC µA 10 000 1 000 100 10 1 VDD 5 5 V VDD 1 6 V ...

Page 209: ...0412 chapter 8 Package 8 1 Plastic Package TQFP15 128pin Unit mm 14 16 65 96 14 16 33 64 INDEX 32 1 128 97 1 0 1 1 2 max 1 0 3 min 0 75 max 0 10 0 4 0 13min 0 23max 0 09min 0 2max The dimensions are subject to change without notice ...

Page 210: ...SIC63616 Rev 1 0 NO P202 3240 0412 8 2 Ceramic Package for Test Samples QFP17 144pin Unit mm 19 20 0 19 22 00 0 25 19 20 0 19 22 00 0 25 0 20 0 50 2 80 Max 0 50 0 20 0 15 73 108 37 72 36 1 144 109 ...

Page 211: ... 0 NO P203 3240 0412 chapter 9 Pad Layout 9 1 Diagram of Pad Layout 3 246mm Y X 0 0 3 124mm 5 10 1 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 Die No 115 Chip thickness 400 µm Pad opening 77 85 µm ...

Page 212: ...N_B P40 P23 SRDY SS FOUT P22 SIN P21 SOUT P20 SCLK P13 TOUT_A P12 EVIN_A P11 RUN LAP P10 RUN LAP P03 RFOUT BZ VDD P02 SEN0 P01 REF0 P00 RFIN0 VSS X 1 471 1 471 1 471 1 471 1 471 1 471 1 471 1 471 1 471 1 471 1 471 1 471 1 471 1 471 1 471 1 471 1 471 1 471 1 140 1 050 0 960 0 870 0 780 0 690 0 600 0 510 0 420 0 330 0 240 0 150 0 060 0 030 0 120 0 210 0 300 0 390 0 480 0 570 0 660 0 750 Y 0 145 0 05...

Page 213: ...ions and method of use Note The S5U1C63000P1 cannot be used for developing the S1C63616 applications A 1 Names and Functions of Each Part A 1 1 S5U1C63000P6 The S5U1C63000P6 board provides peripheral circuit functions of S1C63 Family microcomputers other than the core CPU The following explains the names and functions of each part of the S5U1C63000P6 board Xtal OSC3 CR Adj OSC1 CR Adj Ceramic CN0 ...

Page 214: ... 8 10 12 14 16 LED 5 CR oscillation frequency adjusting control This control allows you to adjust the OSC3 oscillation frequency This function is effective when ceramic oscillation is selected for the OSC3 oscillation circuit by mask option as well as when CR oscillation is selected The oscillation frequency can be adjusted in the range of approx 100 kHz to 8 MHz Note that the actual IC does not o...

Page 215: ...e able to start when you power on the ICE once again In this case temporarily power off the ICE and set CLK to the 32K position and the PRG switch to the Prog position then switch on power for the ICE once again This should allow the debug ger to start up allowing you to download circuit data After downloading the circuit data temporar ily power off the ICE and reset CLK and PRG to the LCLK and th...

Page 216: ...rd socket 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 Connecting a DC bias resistive sensor e g thermistor Capacitor Reference resistor Sensor resistor RFOUT SEN0 REF0 RFIN0 GND CH 0 2 R f converter monitor pins and external part connecting socket Channel 1 These monitor pins are used to check the operation of R f converter channel 1 The socket is used to connect external resistors and a capacitor for ...

Page 217: ...rated with the R f converter socket and monitor pins shown in 1 above Therefore be sure to leave this connector open when R f converter channel 0 is used 4 CN4 LCD connector This is a user connector to output the COM and SEG signals of the LCD driver There are two connec tors provided one is for 1 5 bias and another is for 1 4 bias Be sure to use one of them according to the specification of the t...

Page 218: ...circuit boards to the ICE Installing the S5U1C63000P6 6F632P2 board Set the jig included with the ICE into position as shown in Figure A 2 2 Using this jig as a lever push it toward the inside of the board evenly on the left and right sides After confirming that the board has been firmly fitted into the internal slot of the ICE remove the jig Fig A 2 2 Installing the board Board Dismounting the S5...

Page 219: ...ectrical power VDD 3 3 V T R G O U T S T O P O U T T R C IN B R K IN G N D DIAG OFF ON S5U1C63000H6 EPSON S L P H L T E M U P O W E R LC2 LC1 CN4 1 40 pins Target board S5U1C6F632P2 CN4 80 pins CN1 1 40 pins S5U1C63000P6 CN1 80 pins S5U1C6F632P2 CN3 10 pins CN1 2 40 pins CN3 10 pins CN4 2 40 pins CN4 1 CN1 1 CN1 2 CN3 CN4 2 1 5 bias 1 4 bias Fig A 2 4 Connecting the S5U1C63000P6 and S5U1C6F632P2 t...

Page 220: ...onnected Cannot be connected Cannot be connected Vss Vss No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 40 pin CN1 2 connector Pin name VDD 3 3 V VDD 3 3 V Cannot be connected Cannot be connected Cannot be connected Cannot be connected Cannot be connected Cannot be connected Cannot be connected Cannot be connected VSS VSS Cannot be...

Page 221: ... SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 40 pin CN4 2 connector Pin name SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 Cannot be connected Cannot be connected Cannot be connecte...

Page 222: ... the ICE to the host PC Then turn the host PC and ICE on 3 Invoke the debugger included in the assembler package ver 5 or later for the S5U1C63000H2 ver 9 or later for the S5U1C63000H6 For how to use the ICE and debugger refer to the manuals supplied with the ICE and assembler package 4 Download the circuit data file mot corresponding to the model by entering the following commands in the command ...

Page 223: ... the DOS prompt of Windows 3 Turn the ICE on 4 Configure the RS232C parameters for the host PC as follows C MODE COM1 9600 n 8 1 p 9600 bps 8 bit data 1 stop bit no parity 5 Copy the following files included in the assembler package ver 5 or later to a directory on the hard disk tm63 exe ice63 com i63com o i63par 6 Move to the directory in Step 5 run the TM63 TM63 enters command ready status after...

Page 224: ...erfaced with voltages exceeding VDD by setting the output ports for open drain mode Pull down resistance value The pull down resistance values on S5U1C63000P6 are set to 220 kΩ which differ from those for the actual IC For the resistance values on the actual IC refer to Chapter 7 Electrical Characteristics Note that when using pull down resistors to pull the input pins low the input pins may requi...

Page 225: ...f the OSC3 oscillation circuit If executed simultaneously with a single instruction these operations although good with S5U1C63000P6 may not function properly well with the actual IC Because the logic level of the oscillation circuit is high the timing at which the oscillation starts on S5U1C63000P6 differs from that of the actual IC S5U1C63000P6 contains oscillation circuits for OSC1 and OSC3 Kee...

Page 226: ...cution to break while the R f converter is counting the oscillation the R f converter does not stop counting Note that the R f converter will not able to load a proper result if program execution is resumed from that point The following shows the oscillation characteristics reference value of the R f converter on the S5U1C6F632P2 R f converter oscillation frequency capacitance characteristic refer...

Page 227: ... 80 pin KEL8822E 080 171 F Cable connector 40 pin 3M7940 6500SC 1 pair Cable 40 conductor flat cable 1 pair Interface CMOS interface 3 3 V Length Approx 40 cm I O connection cable 100 pin S5U1C63000P6 connector KEL8830E 100 170L F Cable connector 100 pin KEL8822E 100 171 F Cable connector 50 pin 3M7950 6500SC 1 pair Cable 50 conductor flat cable 1 pair Interface CMOS interface 3 3 V Length Approx ...

Page 228: ...EL8822E 080 171 F Cable connector 40 pin 3M7940 6500SC 1 pair Cable 40 conductor flat cable 1 pair Interface CMOS interface 3 3 V Length Approx 40 cm I O connection cable 10 pin S5U1C6F632P2 connector 3M3654 5002 PL Cable connector 10 pin 3M7910 6500SC Cable 10 conductor flat cable Interface CMOS interface 3 3 V Length Approx 40 cm Accessories 40 pin connector for connecting to target system 3M343...

Page 229: ...Revision History Attachment 1 Rev No Date Page Category Contents Rev 1 0 2011 03 09 All New First edition Revision History ...

Page 230: ... 755 2699 3828 Fax 86 755 2699 3838 EPSON HONG KONG LTD Unit 715 723 7 F Trade Square 681 Cheung Sha Wan Road Kowloon Hong Kong Phone 852 2585 4600 FAX 852 2827 4346 EPSON TAIWAN TECHNOLOGY TRADING LTD 14F No 7 Song Ren Road Taipei 110 TAIWAN Phone 886 2 8786 6688 FAX 886 2 8786 6660 EPSON SINGAPORE PTE LTD 1 HarbourFront Place 03 02 HarbourFront Tower One Singapore 098633 Phone 65 6586 5500 FAX 6...

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