SIC63616-(Rev. 1.0) NO. P132
3240-0412
In master mode, the serial interface uses the internal clock (selected in the clock manager) as the
synchronous clock for serial transfer. The synchronous clock is also output from the SCLK (P20) terminal to
control the external serial interface (slave device). In slave mode, the serial interface inputs the synchronous
clock that is sent by the external serial interface (master device) from the SCLK terminal to perform serial
transfer. Master mode is selected by writing "1" to SMOD, and slave mode is selected by writing "0".
At initial reset, this register is set to "0".
SDP: Data input/output permutation select register (FF59H•D1)
Selects the serial data input/output permutation.
When "1" is written: MSB first
When "0" is written: LSB first
Reading: Valid
Select whether the data input/output permutation will be MSB first or LSB first.
At initial reset, this register is set to "0".
SCPS0, SCPS1: Clock format select register (FF59H•D2, D3)
Selects the timing for reading in the serial data input from the SIN (P22) terminal.
Table 4.10.8.3 Configuration of synchronous clock format
SCPS1
1
1
0
0
SCPS0
1
0
1
0
Polarity
Negative (SCLK)
Negative (SCLK)
Positive (SCLK)
Positive (SCLK)
Phase
Rising edge ( )
Falling edge ( )
Falling edge ( )
Rising edge ( )
• When positive polarity (SCPS1 = "0") is selected for the synchronous clock:
During receiving, the serial data is read into the built-in shift register at the rising edge of the SCLK
signal when the SCPS0 register is "0" or at the falling edge of the SCLK signal when the SCPS0 register is
"1". The shift register is sequentially shifted as the data is fetched.
During transmitting, the serial data output to the SOUT (P21) terminal changes at the rising edge of the
clock input or output from/to the SCLK (P20) terminal. The data in the shift register is shifted at the
rising edge of the SCLK signal when the SCPS0 register is "0" or at the falling edge of the SCLK signal
when the SCPS0 register is "1".
• When negative polarity (SCPS1 = "1") is selected for the synchronous clock:
During receiving, the serial data is read into the built-in shift register at the falling edge of the SCLK
signal when the SCPS0 register is "0" or at the rising edge of the SCLK signal when the SCPS0 register is
"1". The shift register is sequentially shifted as the data is fetched.
During transmitting, the serial data output to the SOUT (P21) terminal changes at the falling edge of the
clock input or output from/to the SCLK (P20) terminal. The data in the shift register is shifted at the
falling edge of the SCLK signal when the SCPS0 register is "0" or at the rising edge of the SCLK signal
when the SCPS0 register is "1".
At initial reset, this register is set to "0".
ENCS: Serial interface enable register (P23 port function selection) (FF5AH•D0)
Enables the serial input/output function of P23. Use this register with ESREADY.
When "1" is written: Enabled (Serial interface)
When "0" is written: Disabled (I/O port)
Reading: Valid
When ENCS is enabled, the P23 terminal can be used as SRDY output or SS input terminal in slave mode
(SMOD = "0").
At initial reset, this register is set to "0".
