SIC63616-(Rev. 1.0) NO. P102
3240-0412
4.9.4 Event counter mode (Timers 0, 2, 4 and 6)
Timer 0 has an event counter function that counts an external clock input to an I/O port. Table 4.9.4.1 lists
the timers and their clock input ports.
Table 4.9.4.1 Event counter clock input port
Control register
EVCNT_A
EVCNT_B
EVCNT_C
EVCNT_D
External clock name
EVIN_A
EVIN_B
EVIN_C
EVIN_D
Input terminal
P12
P41
P42
P43
Timer
Timer 0 (Ch.A)
Timer 2 (Ch.B)
Timer 4 (Ch.C)
Timer 6 (Ch.D)
This function is selected by writing "1" to the counter mode select register EVCNT_A. This sets the
corresponding I/O port to input mode and enables the port to send the input signal to Timer 0 as the count
clock. At initial reset, EVCNT_A is set to "0" and Timer 0 is configured as a normal timer that counts the
internal clock.
In the event counter mode, the clock is supplied to Timer 0 from outside the IC, therefore, the settings of the
count clock frequency select register PTPS0 becomes invalid.
Count down timing can be selected from either the falling or rising edge of the input clock using the pulse
polarity select register PLPUL_A. When "0" is written to the PLPUL_A register, the falling edge is selected,
and when "1" is written, the rising edge is selected. The count down timing is shown in Figure 4.9.4.1.
EVIN_A input
Count data
n
n-1 n-2
n-3
n-4 n-5 n-6
PLPUL_A
EVCNT_A
0
1
1
PTRUN0
Fig. 4.9.4.1 Timing chart in event counter mode
The event counter mode also allows use of a noise reject function to eliminate noise such as chattering on
the external clock (EVIN_A). This function is selected by writing "1" to the timer function select register
FCSEL_A.
When the noise rejector is enabled, an input pulse width for both low and high levels must be 0.98 msec
∗
or more to count reliably. The noise rejector allows the counter to input the clock at the second falling edge
of the internal 2,048 Hz
∗
signal after changing the input level of the EVIN_A input terminal. Consequently,
the pulse width of noise that can reliably be rejected is 0.48 msec
∗
or less.
(
∗
: when f
OSC1
= 32.768 kHz)
Figure 4.9.4.2 shows the count down timing with noise rejector.
Counter
input clock
∗
2
Counter data
n
n-1
n-2
n-3
EVIN_A input
2,048 Hz
∗
1
∗
1
When f
OSC1
= 32.768 kHz
∗
2
When PLPUL_A register is set to "0"
Fig. 4.9.4.2 Count down timing with noise rejector
The operation of the event counter mode is the same as the normal timer except it uses the EVIN_A input
as the clock. Refer to Section 4.9.3, "Basic count operation" for basic operation and control.
