SIC63616-(Rev. 1.0) NO. P125
3240-0412
4.10.6 Data input/output and interrupt function
The serial interface of S1C63616 can input/output data via the internal 8-bit shift register. The shift register
operates by synchronizing with either the synchronous clock output from the SCLK (P20) terminal (master
mode), or the synchronous clock input to the SCLK (P20) terminal (slave mode).
The serial interface generates an interrupt on completion of the 8-bit serial data input/output. Detection of
serial data input/output is done by counting of the synchronous clock SCLK; the clock completes input/
output operation when 8 counts (equivalent to 8 cycles) have been made and then generates an interrupt.
The serial data input/output procedure is explained below:
Serial data output procedure and interrupt
The S1C63616 serial interface is capable of outputting parallel data as serial data, in units of 8 bits.
By setting the parallel data to the data registers SD0–SD3 and SD4–SD7 and writing "1" to SCTRG bit, it
synchronizes with the synchronous clock and the serial data is output to the SOUT (P21) terminal. The
synchronous clock used here is as follows: in master mode, internal clock which is output to the SCLK
(P20) terminal while in slave mode, external clock which is input from the SCLK (P20) terminal.
Shift timing of serial data is as follows:
• When positive polarity (SCPS1 = "0") is selected for the synchronous clock:
The serial data output to the SOUT (P21) terminal changes at the rising edge of the clock input or output
from/to the SCLK (P20) terminal. The data in the shift register is shifted at the rising edge of the SCLK sig-
nal when the SCPS0 register is "0" or at the falling edge of the SCLK signal when the SCPS0 register is "1".
• When negative polarity (SCPS1 = "1") is selected for the synchronous clock:
The serial data output to the SOUT (P21) terminal changes at the falling edge of the clock input or
output from/to the SCLK (P20) terminal. The data in the shift register is shifted at the falling edge of
the SCLK signal when the SCPS0 register is "0" or at the rising edge of the SCLK signal when the SCPS0
register is "1".
When the output of the 8-bit data from SD0 to SD7 is completed, the interrupt factor flag ISIF is set to
"1" and an interrupt occurs. Moreover, the interrupt can be masked by the interrupt mask register EISIF.
However, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" after
output of the 8-bit data.
Serial data input procedure and interrupt
The S1C63616 serial interface is capable of inputting serial data as parallel data, in units of 8 bits.
The serial data is input from the SIN (P22) terminal, synchronizes with the synchronous clock, and is se-
quentially read in the 8-bit shift register. The synchronous clock used here is the internal clock in master
mode or the external clock in slave mode.
Shift timing of serial data is as follows:
• When positive polarity (SCPS1 = "0") is selected for the synchronous clock:
The serial data is read into the built-in shift register at the rising edge of the SCLK signal when the
SCPS0 register is "0" or at the falling edge of the SCLK signal when the SCPS0 register is "1". The shift
register is sequentially shifted as the data is fetched.
• When negative polarity (SCPS1 = "1") is selected for the synchronous clock:
The serial data is read into the built-in shift register at the falling edge of the SCLK signal when the
SCPS0 register is "0" or at the rising edge of the SCLK signal when the SCPS0 register is "1". The shift
register is sequentially shifted as the data is fetched.
When the input of the 8-bit data from SD0 to SD7 is completed, the interrupt factor flag ISIF is set to
"1" and an interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask register
EISIF. However, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1"
after input of the 8-bit data.
The data input in the shift register can be read from data registers SD0–SD7 by software.
