Epson S1C6200, Core Cpu Manual

Page: 63 / 98

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
S1C6200/6200A CORE CPU MANUAL
EPSON
57
3 INSTRUCTION SET
LD X,e
Load immediate data e into X-register
LD X,e
XH
←
e
7
to e
4
, XL
←
e
3
to e
0
1 0 1 1 e
7
e
6
e
5
e
4
e
3
e
2
e
1
e
0
B00H to BFFH
I
5
Not affected
Not affected
Not affected
Not affected
Loads 8-bit immediate data e into register X.
LD X,6FH
XH register 0000 0110
XL register 1011 1111
LD XH,r
Load r-register into XH
LD XH,r
XH
←
r
1 1 1 0 1 0 0 0 0 1 r
1
r
0
E84H to E87H
V
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the r-register into the four high-order bits of register X.
LD XH,A LD XH,MY
XH register 0000 1011 0110
A register 1011 1011 1011
Memory (MY) 0110 0110 0110