Epson S1C6200, Core Cpu Manual

Page: 67 / 98

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
S1C6200/6200A CORE CPU MANUAL
EPSON
61
3 INSTRUCTION SET
NOP5
No operation for 5 clock cycles
NOP5
No operation (5 clock cycles)
1 1 1 1 1 1 1 1 1 0 1 1 FFBH
VI
5
Not affected
Not affected
Not affected
Not affected
Increments the program counter by 1. Has no other effect for 5 clock cycles.
NOP5
PCB 0 0
PCP 0011 0011
PCS 0001 0011 0001 0100
NOP7
No operation for 7 clock cycles
NOP7
No operation (7 clock cycles)
1 1 1 1 1 1 1 1 1 1 1 1 FFFH
VI
7
Not affected
Not affected
Not affected
Not affected
Increments the program counter by 1. Has no other effect for 7 clock cycles.
NOP7
PCB 0 0
PCP 1010 1010
PCS 1001 1001 1001 1010