Epson S1C6200, Core Cpu Manual

Page: 49 / 98

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
S1C6200/6200A CORE CPU MANUAL
EPSON
43
3 INSTRUCTION SET
INC Y
Increment Y-register by 1
INC Y
Y
←
Y + 1
1 1 1 0 1 1 1 1 0 0 0 0 EF0H
VI
5
Not affected
Not affected
Not affected
Not affected
Increments the contents of register Y by 1. This operation does not affect the
flags.
INC Y
Y register 1011 0111 1011 1000
C flag 1 1
Z flag 0 0
JPBA
Indirect jump using registers A and B
JPBA
PCB
←
NBP, PCP
←
NPP, PCSH
←
B, PCSL
←
A
1 1 1 1 1 1 1 0 1 0 0 0 FE8H
VI
5
Not affected
Not affected
Not affected
Not affected
Uses the contents of a- and b-registers to specify the destination address of the
jump. The b-register contains the four high-order bits of the address and the a-
register contains the four low-order bits of the address.
PSET 15H JPBA
PCB 0 0 1
NBP 0 1 1
PCP 1000 1000 0101
NPP 0001 0101 0101
PCS 1001 0000 1001 0001 0000 0110
A register 0110 0110 0110
B register 0000 0000 0000