S1C6200/6200A CORE CPU MANUAL
EPSON
1
1 DESCRIPTION
1 D
ESCRIPTION
The S1C6200/6200A is the Core CPU of the S1C62 Family of CMOS 4-bit single-chip microcomput-
ers. The CPU features a highly-integrated architecture. Memory-mapped peripheral circuits can include
RAM, ROM, I/O ports, interrupt controllers, timers and LCD drivers, depending upon the application.
The memory address space is divided into program and data memory, each with data and address lines.
Program memory consists of on-chip ROM, containing instructions to be executed by the CPU. Data
memory consists of RAM and memory-mapped I/O, as determined by the design of the peripheral cir-
cuitry.
A large memory as well as instructions capable of 8-bit data manipulation enhance the functionality of the
S1C62 Family. Implementation of a common Core CPU ensures that a wide range of application-specific
devices can be designed and fabricated with the minimum turnaround time.
1.1 System Features
• Common Core CPU for all S1C62 Family microcomputers
• UP to 8,192 12-bit words of program memory (ROM)
• UP to 4,096 4-bit words of data memory (RAM/peripheral circuits)
• Memory-mapped I/O
• 5, 7 or 12 clock cycle instructions
• 109 instructions
• Up to 85 levels of subroutine nesting
• 8-bit stack pointer
• Up to 15 interrupt vectors
• Two standby modes
• Low-power CMOS process
1.2 Instruction Set Features
• Four addressing modes: one direct, two indirect, and one stack pointer
• Direct addressing transfers data to and from data memory with a single instruction, resulting in more
efficient code
• 8-bit load instructions and table look-up instructions
• Arithmetic operations in either hexadecimal or decimal
• Arithmetic and logical instructions: addition, subtraction, logical AND, OR, exclusive-OR, comparison
and rotation
1.3 Differences between S1C6200 and S1C6200A
There are some differences in the following operation/circuit between the S1C6200 and the S1C6200A.
For the detailes of each difference, refer to the section enclosed with parentheses.
• Initial setting of D (decimal) flag
(refer to Section 2.5.5, "Initial reset".)
• Interrupt circuit
–
Interrupt timing (refer to Section 2.5.3, "Operation during interrupt generation".)
–
Writing to interrupt mask registers and reading of interrupt flags (refer to Appendix A, "S1C6200A
(Advanced S1C6200) Core CPU".)
Summary of Contents for S1C6200
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