Epson S1C6200, Core Cpu Manual

Page: 86 / 98

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
80
EPSON
S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
SLP
Sleep
SLP
Stop CPU and peripheral oscillator
1 1 1 1 1 1 1 1 1 0 0 1 FF9H
VI
5
Not affected
Not affected
Not affected
Not affected
Stops the CPU and the peripheral oscillator. When an interrupt occurs PCP and
PCS are pushed onto the stack as the return address and the interrupt service
routine is executed.
Instruction State PCP PCS I flag
RUN 0100 0011 0000 1
SLP 0100 0011 0001 1
SLEEP
Interrupt
→
NOP5 RUN
0001 0000 0001 0
SUB r,q
Subtract q-register from r-register
SUB r,q
r
←
r - q
1 0 1 0 1 0 1 0 r
1
r
0
q
1
q
0
AA0H to AAFH
IV
7
Set if a borrow is generated; otherwise, reset.
Set if the result is zero; otherwise, reset.
Not affected
Not affected
Subtracts the contents of the q-register from the r-register.
SUB A,B
A register 1100 1001
B register 0011 0011
C flag 1 0
Z flag 0 0