Epson S1C6200, Core Cpu Manual

Page: 89 / 98

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
S1C6200/6200A CORE CPU MANUAL
EPSON
83
3 INSTRUCTION SET
ABBREVIATIONS
A ............. A register (4 bits)
B ............. B register (4 bits)
M(SP) ..... Contents of the data memory location whose address is specified by stack pointer SP (4 bits)
M(X) ....... Contents of the data memory location whose address is specified by IX (4 bits)
M(Y) ....... Contents of the data memory location whose address is specified by IY (4 bits)
M(n
3
-
0
) .... Contents of the data memory location within the register area 00H to 0FH (4 bits)
MX .......... Data memory location whose address is specified by IX
MY .......... Data memory location whose address is specified by IY
NBP ........ New Bank Pointer (1 bit)
NPP ........ New Page Pointer (4 bits)
PCB ........ Program Counter-Bank (1 bit)
PCP ........ Program Counter-Page (4 bits)
PCS ........ Program Counter-Step (8 bits)
PCSH ..... Four high-order bits of PCS
PCSL ...... Four low-order bits of PCS
RP .......... Register Pointer (4 bits)
SP .......... Stack Pointer (8 bits)
SPH ........ Four high-order bits of SP
SPL ........ Four low-order bits of SP
X ............. Eight low-order bits of IX, that is, XHL
XH .......... Four high-order bits of X
XL ........... Four low-order bits of X
XP .......... Four high-order bits of IX (page part)
Y ............. Eight low-order bits of IY, that is, YHL
YH .......... Four high-order bits of Y
YL ........... Four low-order bits of Y
YP .......... Four high-order bits of IY (page part)
+ ............. Addition
– ............. Subtraction
∧ ...............
Logical AND
∨
............. Logical OR
∀
............. Exclusive-OR
↓
............. Reset flag
↑
............. Set flag
↕
............. Set/reset flag
∗
............. Decimal addition/subtraction