Epson S1C6200, Core Cpu Manual

Page: 36 / 98

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
30
EPSON
S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
ADC XH,i
Add with carry immediate data i to XH
ADC XH,i
XH
←
XH + i
3
to i
0
+ C
1 0 1 0 0 0 0 0 i
3
i
2
i
1
i
0
A00H to A0FH
IV
7
Set if a carry is generated; otherwise, reset.
Set if the result is zero; otherwise, reset.
Not affected
Not affected
Adds the carry bit and immediate data i to XH, the four high-order bits of XHL.
ADC XH,2 ADC XH,4
XH register 1001 1100 0000
C flag 1 0 1
Z flag 0 0 1
ADC XL,i
Add with carry immediate data i to XL
ADC XL,i
XL
←
XL + i
3
to i
0
+ C
1 0 1 0 0 0 0 1 i
3
i
2
i
1
i
0
A10H to A1FH
IV
7
Set if a carry is generated; otherwise, reset.
Set if the result is zero; otherwise, reset.
Not affected
Not affected
Adds the carry bit and immediate data i to XL, the four low-order bits of XHL.
ADC XL,3 ADC XL,0EH
XL register 0000 0100 0010
C flag 1 0 1
Z flag 1 0 0