Epson S1C6200, Core Cpu Manual

Page: 53 / 98

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
S1C6200/6200A CORE CPU MANUAL
EPSON
47
3 INSTRUCTION SET
LD A,Mn
Load memory into A-register
LD A,Mn
A
←
M(n
3
to n
0
)
1 1 1 1 1 0 1 0 n
3
n
2
n
1
n
0
FA0H to FAFH
IV
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the data memory location addressed by Mn into the A-
register.
LD A,M5 LD A,M6
A register 0100 1111 0100
Memory (05H) 1111 1111 1111
Memory (06H) 0100 0100 0100
LD B,Mn
Load memory into B-register
LD B,Mn
B
←
M(n
3
to n
0
)
1 1 1 1 1 0 1 1 n
3
n
2
n
1
n
0
FB0H to FBFH
IV
5
Not affected
Not affected
Not affected
Not affected
Loads the contents of the data memory location addressed by Mn into the B-
register.
LD B,M7 LD B,M8
B register 0100 0110 1010
Memory (07H) 0110 0110 0110
Memory (08H) 1010 1010 1010