Epson S1C6200, Core Cpu Manual

Page: 34 / 98

Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
Source Format:
Operation:
OP-Code:
Type:
Clock Cycles:
Flag:
Description:
Example:
MSB LSB
MSB LSB
C –
Z –
D –
I –
C –
Z –
D –
I –
28
EPSON
S1C6200/6200A CORE CPU MANUAL
3 INSTRUCTION SET
ACPX MX,r
Add with carry r-register to M(X), increment X by 1
ACPY MY,r
Add with carry r-register to M(Y), increment Y by 1
ACPX MX,r
M(X)
←
M(X) + r + C, X
←
X + 1
1 1 1 1 0 0 1 0 1 0 r
1
r
0
F28H to F2BH
V
7
Set if a carry is generated; otherwise, reset.
Set if the result is zero; otherwise, reset.
Not affected
Not affected
Adds the carry bit and the contents of the r-register to the data memory location
addressed by IX. X is incremented by one. Incrementing X does not affect the
flags.
ACPX MX,A ACPX MX,MY
X register 1010 0000 1010 0001 1010 0010
Y register 0100 0110 0100 0110 0100 0110
Memory (A0H) 0110 1111 1111
Memory (A1H) 0011 0011 0111
Memory (46H) 0100 0100 0100
A register 1000 1000 1000
C flag 1 0 0
Z flag 0 0 0
ACPY MY,r
M(Y)
←
M(Y) + r + C, Y
←
Y + 1
1 1 1 1 0 0 1 0 1 1 r
1
r
0
F2CH to F2FH
V
7
Set if a carry is generated; otherwise, reset.
Set if the result is zero; otherwise, reset.
Not affected
Not affected
Adds the carry bit and the contents of the r-register to the data memory location
addressed by IY. Y is incremented by one. Incrementing Y does not affect the
flags.
ACPY MY,A ACPY MY,MX
X register 0010 0001 0010 0001 0010 0001
Y register 0000 1110 0000 1111 0001 0000
Memory (0EH) 1000 1011 1011
Memory (0FH) 0100 0100 1010
Memory (21H) 0110 0110 0110
A register 0010 0010 0010
C flag 1 0 0
Z flag 0 0 0