Embedded Solutions
Page 34
BA22_CHAN_LINE_LENGTH
[0x2C] Tx Line Length(read/write)
Tx Line Length Register
Data Bit
Description
31-0
Amount of data required to start transmission
Figure 21 PcieBiSerialDb37BA22 TX Line Length Register
This read/write port accesses the Line Length register. Set the number of pixels per line
to be transmitted with this register. For each pixel, 7 clock periods will be used to
transmit the 14 bits.
BA22_CHAN_IDLE_LENGTH
[0x30] Tx Idle Length(read/write)
Tx Idle Length Register
Data Bit
Description
31-0
Amount of data required to start transmission
Figure 22 PcieBiSerialDb37BA22 TX Idle Length Register
This read/write port accesses the Idle Length register. Set the number of pixels times
per line to be transmitted with this register. For each pixel, 7 clock periods will be used
to transmit the 14 bits. Data is set to ‘0’ for each bit location and the sync is also set to
the IDLE pattern [all ‘0’].