Embedded Solutions
Page 17
Packet loaded if shorter than the FIFO size. For reception it means that the FIFO is
under HW control and the delay from starting reception to starting DMA won’t cause an
overflow condition.
DMA can be programmed with a specific length. The length can be as long as you want
within standard memory limitations. At the end of the DMA transfer the Host will receive
an interrupt. The Transmitter can be stopped, and the FIFO reset to clear out any
untransmitted data. For on-the-fly processing multiple shorter DMA segments can be
programmed; at the interrupt restart DMA to point at the alternate segment to allow
processing on the previous one. This technique is sometimes referred to as “ping-
pong”.
Please see the channel control register bit maps for more information.
