Embedded Solutions
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BA22_CHAN_TX_FIFO_COUNT
[0x8] TX [Target] FIFO data count (read only)
TX FIFO Data Count Port
Data Bit
Description
31-0
TX Data Words Stored
Figure 13 PcieBiSerialDb37BA22 TX FIFO data count Port
This read-only register port reports the number of 32-bit data words in the Transmit
FIFO.
BA22_CHAN_RD_DMA_PNTR
[0xC] Read DMA Pointer (write only)
BurstIn DMA Pointer Address Register
Data Bit
Description
31-2
First Chaining Descriptor Physical Address
1
direction [1]
0
end of chain
Figure 14 PcieBiSerialDb37BA22 Read DMA pointer register
This write-only port is used to initiate a scatter-gather read [RX] DMA. When the
address of the first chaining descriptor is written to this port, the DMA engine reads
three successive long words beginning at that address. Essentially this data acts like a
chaining descriptor value pointing to the next value in the chain.
The first is the address of the first memory block of the DMA buffer to write data from
the device to, the second is the length in bytes of that block, and the third is the address
of the next chaining descriptor in the list of buffer memory blocks. This process is
continued until the end-of-chain bit in one of the next pointer values read indicates that it
is the last chaining descriptor in the list.
All three values are on LW boundaries and are LW in size. Addresses for successive
parameters are incremented. The addresses are physical addresses the HW will use
on the PCI bus to access the Host memory for the next descriptor or to read the data to
be transmitted. In most OS you will need to convert from virtual to physical. The length
parameter is a number of bytes, and must be on a LW divisible number of bytes.
Status for the DMA activity can be found in the channel control register and channel
status register.
