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during Idle time. Idle will be sent for the programmed length between lines [Idle Time]
and between frames as programmed with the difference in frame time and the master
sync period.

CHAN_TX_DataPat

[0x4C] Tx Data Pattern (read/write)

Tx Data Pattern Register

Data Bit

Description

7-0

Control Pattern to send during Data

Figure 29 PcieBiSerialDb37BA22 TX Data Pattern Register

This read/write port accesses the Data Pattern register. Set the control data to send
during Data transmission time. The Data control word will be sent on the control line in
parallel with the transmitted data.

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Summary of Contents for PCIeBiSerialDb37-BA22

Page 1: ...CA 95060 831 457 8891 Fax 831 457 4793 http www dyneng com sales dyneng com Est 1988 User Manual PCIeBiSerialDb37 BA22 Image Data Transmit Receive Port 2 bit serial with clock and sync PCIe 4 lane Mo...

Page 2: ...ice Furthermore Dynamic Engineering assumes no liability arising out of the application or use of the device described herein The electronic equipment described herein generates uses and can radiate r...

Page 3: ...25 BA22_CHAN_WR_DMA_PNTR 29 BA22_CHAN_TX_FIFO_COUNT 30 BA22_CHAN_RD_DMA_PNTR 30 BA22_CHAN_RX_FIFO_COUNT 31 BA22_CHAN_FIFO 31 BA22_CHAN_TX_AMT_LVL 32 BA22_CHAN_RX_AFL_LVL 32 BA22_CHAN_READY_CNT 33 BA22...

Page 4: ...ions Page 4 APPLICATIONS GUIDE 40 Interfacing 40 Construction and Reliability 41 Thermal Considerations 41 Warranty and Repair 42 Service Policy 42 Out of Warranty Repairs 42 SPECIFICATIONS 43 ORDER I...

Page 5: ...5 PCIEBISERIALDB37BA22 RX FIFO DATA COUNT PORT 31 FIGURE 16 PCIEBISERIALDB37BA22 RX TX FIFO PORT 31 FIGURE 17 PCIEBISERIALDB37BA22 TX ALMOST EMPTY LEVEL REGISTER 32 FIGURE 18 PCIEBISERIALDB37BA22 RX A...

Page 6: ...dance The IO s are buffered from the FPGA with differential transceivers The transceivers can be populated with LVDS or RS 485 compatible devices The power plane for the transceivers is isolated to al...

Page 7: ...PreAmble are programmable The rate of transmission and the dimensions of the transmission are programmable Since the data is serialized as 2 7 bit streams from 1 14 bit word data is packed 2 pixels p...

Page 8: ...ed with new JED files using the driver The hardware supports programming the PLL with an I2C bus 2 256x32 FIFO s and a state machine The UserAp and driver provide a reference for programming the PLL T...

Page 9: ...rage FIFO The reference rate of the input to the FIFO is the receive clock The read side of the first receive FIFO is tied to the input side of a 1Kx32 FIFO The second FIFO is used to support the rece...

Page 10: ...functions are designed into the channel and the PLL programming switch and other common or basic functions are in the base design From a software perspective the design can be treated as Flat or as a...

Page 11: ...engths than the OS max and for OS situations where the memory is not contiguous With Windows lengths of 4K are common while Linux can provide much larger spaces Larger spaces are more efficient as the...

Page 12: ...to the Sync unless that is also zero pixels in which case it starts with the Data Control pattern Some camera interfaces use a 1 pixel sync followed by some number of IDLE characters to form a sync p...

Page 13: ...rate The Blanking time is the difference in the frame repetition rate and the size of the image and idle time It is programmed in terms of the reference rate clock The time does not have to be an int...

Page 14: ...is for the local decoding performed within PcieBiserialDb37BA22 The addresses are all offsets from a base address Dynamic Engineering prefers a long word oriented approach because it is more consisten...

Page 15: ...used for Urgent and pulsed interrupt define CHAN_RX_AFL 0x00000018 6 Rx almost full count register define CHAN_READY_CNT 0x00000024 9 Amount of data in pipeline before Tx can start define CHAN_FRAME_R...

Page 16: ...that can be programmed into the PLL The IO for the BA22 direction and termination are hardwired in this design The ports are unidirectional and initialization is simplified with this approach The cont...

Page 17: ...want within standard memory limitations At the end of the DMA transfer the Host will receive an interrupt The Transmitter can be stopped and the FIFO reset to clear out any untransmitted data For on...

Page 18: ...rmal operation The PLL is programmed with the output file generated by the Cypress PLL programming tool CY3672 R3 01 Programming Kit or CyberClocks R3 20 00 Cypress may update the revision from time t...

Page 19: ...alDb37BA22 physical card matches each PCI address assigned in a system with multiple cards installed The DIPswitch can also be used for other purposes software revision etc The switch shown would read...

Page 20: ...iting data to the PLL is empty When cleared at least 1 location is filled PllRdFifoMt when set indicates the FIFO associated with reading data from the PLL is empty When cleared at least 1 location is...

Page 21: ...the disable The Length is the number of bytes in the data portion of the message 1 Please note The PLL s have two data sets written to two address offsets per PLL programmed The UserAp automatically...

Page 22: ...ol Register read write Channel Control Register Data Bit Description 31 25 spare 24 TxInitialIdle 23 spare 22 RxDataOrder 21 CaptureAll 20 RxStart 19 RxOflInt 18 TxFrameCntLd 17 TxFrameCntEn 16 TxData...

Page 23: ...ware some control over how DMA requests are processed and to allow for a higher rate channel to have a higher priority over other lower rate channels ByPass when set allows the FIFO to be used in a lo...

Page 24: ...when set allows the synchronization counter to run The counter runs from 0 to the programmed end count and repeats A pulse is output at the end of each counting cycle TxFrameCntLd loads the Counter to...

Page 25: ...curred 14 Write DMA Interrupt Occurred 13 Read DMA Error Occurred 12 Write DMA Error Occurred 11 RxAFLvlIntLat 10 TxAELvlIntLat 9 EXT FIFO 1 MT 8 EXT FIFO 0 MT 7 spare 6 Rx FIFO Full 5 Rx FIFO Almost...

Page 26: ...ad there is room for at least one more data word in the FIFO If the FIFO is full when time to write received data to the FIFO an overflow error is declared Tx FIFO Empty When a one is read the FIFO co...

Page 27: ...IDLE state and 0 when processing a DMA A new DMA should not be launched until the State machine is back in the IDLE state Please note that the direction implied in the name has to do with the DMA dire...

Page 28: ...t Full based on the programmed count The software can do a looped read or use DMA to unload the programmed count amount of data to the system memory The signal is latched and can be cleared via write...

Page 29: ...of buffer memory blocks This process is continued until the end of chain bit in one of the next pointer values read indicates that it is the last chaining descriptor in the list All three values are...

Page 30: ...acts like a chaining descriptor value pointing to the next value in the chain The first is the address of the first memory block of the DMA buffer to write data from the device to the second is the le...

Page 31: ...line The maximum count is the FIFO size plus 4 BA22_CHAN_FIFO 0x10 Write TX Read RX FIFO Port RX and TX FIFO Port Data Bit Description 31 0 FIFO data word Figure 16 PcieBiSerialDb37BA22 RX TX FIFO Por...

Page 32: ...be set The register is R W for 32 bits The mask is valid for a size matching the depth of the FIFO BA22_CHAN_RX_AFL_LVL 0x18 Rx almost full read write Rx Almost Full Level Register Data Bit Descriptio...

Page 33: ...Db37BA22 TX Frame Reference Register This read write port accesses the Frame Reference register PLLA clock is the time base 73 636 MHz for BA22 This corresponds to 13 58 nS per period The Frame repeti...

Page 34: ...r each pixel 7 clock periods will be used to transmit the 14 bits BA22_CHAN_IDLE_LENGTH 0x30 Tx Idle Length read write Tx Idle Length Register Data Bit Description 31 0 Amount of data required to star...

Page 35: ...Amble read write Tx PreAmble Pattern Register Data Bit Description 7 0 Control Pattern to send during PreAmble Figure 24 PcieBiSerialDb37BA22 TX PreAmble Pattern Register This read write port accesses...

Page 36: ...kipped CHAN_TX_SyncLen 0x44 Tx Sync Length read write Tx Sync Length Register Data Bit Description 15 0 Number of Sync pixels to send Figure 27 PcieBiSerialDb37BA22 TX Sync Length Register This read w...

Page 37: ...iod CHAN_TX_DataPat 0x4C Tx Data Pattern read write Tx Data Pattern Register Data Bit Description 7 0 Control Pattern to send during Data Figure 29 PcieBiSerialDb37BA22 TX Data Pattern Register This r...

Page 38: ...mes can be used to accommodate a different set up The loop back plug is a DB37 connector with the interconnections protected with a connector shell Twisted Pair wiring is used For short cables Cat5e c...

Page 39: ...O_6m RxPDataL 7 8 IO_7p RxPClk IO_7m RxPClk 26 27 IO_8p unused IO_8m unused 9 10 IO_9p unused IO_9m unused 28 29 IO_10p unused IO_10m unused 11 12 IO_11p unused IO_11m unused 30 31 IO_12p unused IO_12...

Page 40: ...ng areas by powering the equipment together and by having a good ground reference Keep cables short Flat cables even with alternate ground lines are not suitable for long distances In addition series...

Page 41: ...CIe is secured against the chassis with the connectors and front panel If more security against vibration is required a chassis with top side support can be used The PCIeBiSerialDb37 has a wider keep...

Page 42: ...harges must accompany the return Dynamic Engineering will not be responsible for damages due to improper packaging of returned items For service on Dynamic Engineering Products not purchased directly...

Page 43: ...ters IO Read Back registers FIFO R W 32 bit boundaries Initialization Programming procedure documented in this manual Access Modes LW to registers read write to most registers Access Time Frame to TRD...

Page 44: ...formal coating ET to change to industrial Temp 40 85C Dbterm37 37 position terminal block with DB37 connector http www dyneng com DBterm37 html Dbcabl37 DB37 cable compatible with PCIeBiSerialDB37 Twi...

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