Embedded Solutions
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transmitted. Data is held as “00” during transmission.
CHAN_TX_SyncPat
[0x40] Tx Sync (read/write)
Tx Sync Pattern Register
Data Bit
Description
7-0
Control Pattern to send during Sync
Figure 26 PcieBiSerialDb37BA22 TX Sync Pattern Register
This read/write port accesses the Sync Pattern register. Set the control data to send
during Sync time. Sync will be sent when the Master Sync has been detected for
SyncLen pixels. If programmed to 0 length the Sync is skipped.
CHAN_TX_SyncLen
[0x44] Tx Sync Length(read/write)
Tx Sync Length Register
Data Bit
Description
15-0
Number of Sync pixels to send
Figure 27 PcieBiSerialDb37BA22 TX Sync Length Register
This read/write port accesses the Sync Length register. If programmed to 0 length the
Sync is skipped. If set to a non-zero length, that number of PreAmble pixels is
transmitted. Data is held as “00” during transmission.
CHAN_TX_IdlePat
[0x48] Tx Idle Pattern(read/write)
Tx IDLE Pattern Register
Data Bit
Description
7-0
Control Pattern to send during IDLE
Figure 28 PcieBiSerialDb37BA22 TX Idle Pattern Register
This read/write port accesses the Idle Pattern register. Set the control data to send