Embedded Solutions
Page 20
BA22_BASE_STATUS
[$08 Board level Status Port read only]
DATA BIT
DESCRIPTION
31-19
set to ‘0
18-16
PllPckDnCnt
15-13
set to ‘0’
12
PllNakLat
11
PllPacketDoneLat
10
PllRdFifoMt
9
PllWrFifoMt
8
Pll Idle
7-1
set to ‘0’, reserved for additional channels
0
Unmasked Ch0 Interrupt
Figure 8 PcieBiSerialDb37BA22 Status Port Bit Map
Channel Interrupt – The local interrupt status from the channel. Each channel can have
different interrupt sources. DMA Write or DMA Read or IntForce or TX/RX request are
typical sources. Polling can be accomplished using the channel status register and
leaving the channel interrupt disabled.
Pll Idle when set indicates the PLL State-Machine is in the IDLE state.
PllWrFifoMt when set indicates the FIFO associated with writing data to the PLL is
empty. When cleared at least 1 location is filled.
PllRdFifoMt when set indicates the FIFO associated with reading data from the PLL is
empty. When cleared at least 1 location is filled.
PllPacketDoneLat is set and held when the PLL completes an operation. For example a
write to the PLL when completed will set this bit. This is a sticky bit. Cleared by writing
to the same address with this bit set.
PllNakLat when set indicates an operation to the PLL was not acknowledged. Usually
this is due to an improper address being used to communicate with the PLL. This is a
sticky bit. Clear by writing back with this bit position set.
PllPckDnCnt is a 3 bit count indicating how many operations have completed. Each
write operation takes 1 and each read takes 2 since the address is first written and then
the data read. The count can be used as a condition to know when a transfer is
completed. Count is cleared when the PllPacketDoneLat bit is cleared.
