Embedded Solutions
Page 5
FIGURE 1 PCIEBISERIALDB37BA22 BLOCK DIAGRAM
8
FIGURE 2 PCIEBISERIALDB37BA22 TIMING DIAGRAM
11
FIGURE 3 PCIEBISERIALDB37BA22 IMAGE DIAGRAM
12
FIGURE 4 PCIEBISERIALDB37BA22 INTERNAL ADDRESS MAP BASE FUNCTIONS
14
FIGURE 5 PCIEBISERIALDB37BA22 CHANNEL ADDRESS MAP
15
FIGURE 6 PCIEBISERIALDB37BA22 CONTROL BASE REGISTER BIT MAP
18
FIGURE 7 PCIEBISERIALDB37BA22 ID AND SWITCH BIT MAP
19
FIGURE 8 PCIEBISERIALDB37BA22 STATUS PORT BIT MAP
20
FIGURE 9 PCIEBISERIALDB37BA22 PLL FIFO PORT BIT MAP
21
FIGURE 10 PCIEBISERIALDB37BA22 CHANNEL CONTROL REGISTER
22
FIGURE 11 PCIEBISERIALDB37BA22 CHANNEL STATUS PORT
25
FIGURE 12 PCIEBISERIALDB37BA22 WRITE DMA POINTER REGISTER
29
FIGURE 13 PCIEBISERIALDB37BA22 TX FIFO DATA COUNT PORT
30
FIGURE 14 PCIEBISERIALDB37BA22 READ DMA POINTER REGISTER
30
FIGURE 15 PCIEBISERIALDB37BA22 RX FIFO DATA COUNT PORT
31
FIGURE 16 PCIEBISERIALDB37BA22 RX/TX FIFO PORT
31
FIGURE 17 PCIEBISERIALDB37BA22 TX ALMOST EMPTY LEVEL REGISTER
32
FIGURE 18 PCIEBISERIALDB37BA22 RX ALMOST FULL LEVEL REGISTER
32
FIGURE 19 PCIEBISERIALDB37BA22 TX READY COUNT REGISTER
33
FIGURE 20 PCIEBISERIALDB37BA22 TX FRAME REFERENCE REGISTER
33
FIGURE 21 PCIEBISERIALDB37BA22 TX LINE LENGTH REGISTER
34
FIGURE 22 PCIEBISERIALDB37BA22 TX IDLE LENGTH REGISTER
34
FIGURE 23 PCIEBISERIALDB37BA22 TX FRAME LENGTH REGISTER
35
FIGURE 24 PCIEBISERIALDB37BA22 TX PREAMBLE PATTERN REGISTER
35
FIGURE 25 PCIEBISERIALDB37BA22 TX PREAMBLE LENGTH REGISTER
35
FIGURE 26 PCIEBISERIALDB37BA22 TX SYNC PATTERN REGISTER
36
FIGURE 27 PCIEBISERIALDB37BA22 TX SYNC LENGTH REGISTER
36
FIGURE 28 PCIEBISERIALDB37BA22 TX IDLE PATTERN REGISTER
36
FIGURE 29 PCIEBISERIALDB37BA22 TX DATA PATTERN REGISTER
37
FIGURE 24 PCIEBISERIALDB37BA22 LOOP-BACK WIRING DIAGRAM
38
FIGURE 25 PCIEBISERIALDB37BA22 FRONT PANEL INTERFACE
39
List of Figures
