Embedded Solutions
Page 23
FIFO Transmitter/Receiver Reset: When set to a one, the transmit and/or receive FIFOs
will be reset. When these bits are zero, normal FIFO operation is enabled. In addition
the Transmit and Receive State Machines are also reset.
Write/Read DMA Interrupt Enable: These two bits, when set to one, enable the
interrupts for DMA writes and reads respectively.
Channel Interrupt Enable: When this bit is set to a one, all enabled interrupts (except
the DMA interrupts) will be gated through to the PCI interface level of the design; when
this bit is a zero, the interrupts can be used for status without interrupting the host. The
channel interrupt enable is for the channel level interrupt sources only.
Force Interrupt: When this bit is set to a one, a system interrupt will occur provided the
Channel Interrupt enable is set. This is useful for interrupt testing.
InUrgent / OutUrgent when set causes the DMA request to have higher priority under
certain circumstances. Basically when the TX FIFO is almost empty and InUrgent is set
the TX DMA will have higher priority than it would otherwise get. Similarly if the RX
FIFO is almost full and OutUrgent is set the read DMA will have higher priority. The
purpose is to allow software some control over how DMA requests are processed and to
allow for a higher rate channel to have a higher priority over other lower rate channels.
ByPass when set allows the FIFO to be used in a loop-back mode internal to the device.
A separate state-machine is enabled when ByPass is set and the TX and RX are not
enabled. The state-machine checks the TX and RX FIFO’s and when not empty on the
TX side and not Full on the RX side moves data between them. Writing to the TX FIFO
allows reading back from the RX side. An example of this is included in the Driver
reference software.
FIFO External Reset: When set to ‘1’, the External FIFO’s will be reset. When cleared
the External FIFO is enabled.
TxStart when set to ‘1’ provides the SW enable to the Tx state-machine to begin data
transfer. The state-machine waits for the combination of SW enable, Data Ready, and
Sync Pulse. Data Ready occurs when the Tx FIFO chain has enough data loaded.
The Sync Pulse re-occurs on the basis programmed with SW. Please see the other
register definitions for more detail. When disabled the state-machine will return to the
Idle state. The state-machine will complete the current task before returning. Reset
can be used to abort if the SW wants to force back to the Idle state.
TxInt when set to ‘1’ enables the transmitter to cause an interrupt for each frame
completed. Depending on the system this can provide a heartbeat, trigger more data to
be loaded etc.