Embedded Solutions
Page 11
being available. LED’s are provided to show the active PCIe lanes.
Designs implemented on PC104p, PMC, IP and PCIe versions of the BiSerial family can
in large part be ported between platforms. If you see what you need in one version and
prefer it on another please contact Dynamic Engineering about porting the design. In
most cases it will require a recompile of the VHDL and not much more. We do a lot of
“just like but different “ adaptations for our clients. Please contact us to help you with a
successful special adaptation of off- the-shelf hardware.
The DMA programmable length is 32 bits => longer than most computer OS will allow in
one segment of memory. The DMA is scatter gather capable for longer lengths than the
OS max and for OS situations where the memory is not contiguous. With Windows®
lengths of 4K are common while Linux can provide much larger spaces. Larger spaces
are more efficient as there are fewer initialization reads and reduced overhead on the
bus. A single interrupt can control the entire transfer. Head to tail operation can also be
programmed with two memory spaces with two interrupts per loop.
The hardware is organized with the IO function in channel 0 and the card level functions
in the “base”. The driver provides the ability to find the hardware and to allocate
resources to use the base and channel functions.
The basic use of the interface is to facilitate data transfer between the host and the
remote target.
Figure 2 PCIEBISERIALDB37BA22 Timing Diagram
The clock is free running. The transmitter provides data with close to 50% duty cycle –
CLK
DATAL
6
5
4
3
2
1
0
DATAU
13
12
11
10
9
8
7
SYNC
F
6
13
