Embedded Solutions
Page 8
Figure 1 PcieBiSerialDb37BA22 Block Diagram
BA22 supports transmission and reception of serialized 2 bit wide data. The Data
transfer is controlled with a continuous clock plus sync pattern. The transmitter uses
the rising edge of the clock. The receiver uses the falling edge of the clock. The
serialized data is deserialized and stored as pixels, two per LW. The upper two bits per
stored pixel are used to mark frames and lines to allow for SW synchronization.
The PLL can be used to create a Tx clock reference. The control is via SW. The PLL is
referenced to 25 MHz. and can be programmed with new .JED files using the driver.
The hardware supports programming the PLL with an I2C bus , 2-256x32 FIFO’s and a
state-machine. The UserAp and driver provide a reference for programming the PLL.
The .JED file is the output from the Cypress 22393 programming tool. The Dynamic
Engineering SW “cracks” the .JED and loads the appropriate portions into the storage
elements for the state-machine to transfer to the PLL.
The transmitter hardware waits until the SW enable is set, the programmed minimum
data in the TX FIFO has been met, and the sync pulse is received [from the local timer].
Once in transmission the sync pulse and a non empty FIFO are the requirements to
(2 x 4 x LVDS)
termination
PCI IF
Data Flow
Control
PLL
TX FIFO
~262K x 32
TX State
Machine
RX FIFO
5K x 32
RX State
Machine
BA22
PCIe x4
PCI
Bridge
