Embedded Solutions
Page 7
board. “BA22” is set to use the LVDS standard, and supports one Transmit and one
Receive channel. The transmitter and receiver are designed to interface with a 2 bit
serial data stream with reference sync and clk. The base frequency is 73.636 MHz.
The transmit frequency is programmable using the A output from the PLL.
The receive side auto-bauds to the incoming rate. The data is deserialized and when
the synchronization pattern indicates, captured into a FIFO. The captured data is
available for DMA transfer to the host memory.
The Transmitter is supported with a combination of discrete 128Kx32 and BRAM based
FIFO’s for a total of 268,285 x 32 FIFO. Using DMA transfers the transmit side can
provide a continuous flow of data at the output. The transmitter has a programmable
frame start reference as well as programmable Line, Idle, Frame, Sync and PreAmble
lengths. In addition the control pattern for IDLEs, DATA, SYNC, and PreAmble are
programmable. The rate of transmission, and the dimensions of the transmission are
programmable.
Since the data is serialized as 2 -7 bit streams from 1 -14 bit word data is packed 2
pixels per LW. With the standard transmission rate of 73.636 MHz the effective unload
rate is (73.636/7)*2 or 5.259 MLW/S. The input side capability with DMA is 33 MLW/S
before overhead and perhaps 20 MLW/S with overhead.
The transmitter has an additional programmable feature of a minimum FIFO count
before starting transmission. By setting the count to be fairly large, the FIFO can be
effectively used as a timing buffer to insure a constant flow of data . With the large
multiplier (DMA vs Transmission) the “fill side” will always be able to keep up with the
transmitter on an overall basis. The FIFO will insure short term delays in processing do
not cause under-run issues. 268,285 x 2 * 3/4 * 7 * 13.58 => 38 mS of storage. [total
TX FIFO (LW) * 2 Pixels/LW * fraction filled when OS system delay happens* effective
bits per pixel [14 but 2 streams] * period of transmission clock]
The Receiver and Transmitter are separately supported with scatter gather capable
DMA engines.
