Digi Rabbit 5000, User Manual

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70 Rabbit 5000 Microprocessor User’s Manual
5.4 Register Descriptions
MMU Instruction/Data Register (MMIDR) (Address = 0x0010)
Bit(s) Value Description
7 0
Internal I/O addresses are decoded using only the lower eight bits of the internal
I/O address bus. This restricts internal I/O addresses to the range 0x0000–
0x00FF.
1
Internal I/O addresses are decoded using all 15 bits of the address internal I/O
address bus. This option must be selected to access internal I/O addresses of
0x0100 and higher.
6 This bit is reserved an must be written with zero.
5 0
Enable A16 and bank select address MSB inversion independent of
instruction/data.
1
Enable A16 and bank select address MSB inversion for data accesses only. This
enables the instruction/data split.
4 0 Normal /CS1 operation.
1
Force /CS1 always active. This will not cause any conflicts as long as the
memory using /CS1 does not also share an output enable or write enable with
another memory.
3 0 Normal operation.
1
For a data segment access, invert bank select address MSB before MBxCR
decision.
2 0 Normal operation.
1 For a data segment access, invert A16
1 0 Normal operation.
1
For a root segment access, invert bank select address MSB before MBxCR
decision.
0 0 Normal operation.
1 For a root segment access, invert A16
Stack Segment Register (STACKSEG) (Address = 0x0011)
Bit(s) Value Description
7:0 Read The current contents of this register are reported.
Write
Eight LSBs (MSBs are set to zero by write) of physical address offset to use if
SEGSIZ[7:4]

Addr[15:12] < 0xE