Digi Rabbit 5000, User Manual

Page: 187 / 414

Chapter 18 Serial Ports E – F 187
18. S
ERIAL
P
ORTS
E – F
18.1 Overview
Serial Ports E and F are identical to each other, and their asynchronous operation is identi-
cal to that of Serial Ports A – D except for the source of the data clock, the buffer sizes,
and the transmit, receive, and clock pins. Each serial port can be used in the asynchronous
or the HDLC mode with an internal or external clock.
In the asynchronous mode, either 7 or 8 data bits can be transferred, and both a parity bit
and/or ninth data bit can be appended as well. Parity and the ninth data bits are also
detected when they are received. The asynchronous mode is full-duplex.
The transmit and receive buffers of Serial Ports E and F have 4 bytes each; this reduces the
interrupt overhead requirements because an interrupt does not have to be generated as
often. A serial port interrupt is generated whenever at least one byte is available in the
receive buffer or whenever a byte is shifted out of the transmit buffer.
The status of each serial port is available in its Serial Port Status Register (SxSR), and
contains information on whether a received byte is available, the receive buffer was over-
run, a parity error was received, the transmit buffer is empty or busy sending a byte, and
the state of the ninth data bit (whether it is an address bit or a stop bit).
Serial Ports E and F support the HDLC mode with either an internal or an external clock;
separate pins may be used for the transmit and receive clocks, or the transmit and receive
clocks may be combined onto a single pin. The HDLC packet flag encapsulation, flag
escapes, and CRC calculation and check are handled automatically by the processor. The
serial port can detect end-of-frame, short-frame, and CRC errors. Interrupts are generated
by the reception of an end-of-frame, at the end of a transmission of a CRC, by an abort
sequence, or by a closing flag. Transmit and receive operations are essentially automatic.
The standard CRC-CCITT polynomial ( x
16
+ x
12
+ x
5
+ 1) is implemented for the CRC,
with the generator and checker preset to all ones.
It is possible to send packets with or without a CRC appended. It is also possible to select
whether an abort or flag will be transmitted if the transmitter underflows. A packet under
transition can be aborted and the abort pattern sent. The idle condition of the line can be
flags or all ones.
Several types of data encoding are available in HDLC mode: NRZ, NRZI, biphase-level
(Manchester), biphase-space (FM0), and biphase-mark (FM1). IrDA-compliant RZI