Digi Rabbit 5000, User Manual

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Chapter 21 DMA Channels 229
21. DMA C
HANNELS
21.1 Overview
There are eight independent DMA channels on the Rabbit 5000. All eight channels are
identical, and are capable of transferring data to or from memory, external I/O, or internal
I/O. The priority between the channels can be either fixed or rotating, and the DMA use of
the bus can be limited to guarantee interrupt latency or CPU throughput. The DMA channels
are capable of special handling for the last byte of data when sending data to selected
internal I/O addresses (such as the HDLC serial ports or to the Ethernet peripheral), and
can also transfer end-of-frame status after transferring data from selected internal I/O
addresses.
The DMA channels can watch the data being transferred, and can terminate a transfer
when a particular byte is matched. A mask is available for the byte match to allow termi-
nation only on particular bit settings in the data instead of an exact byte match.
Memory-to-memory transfers proceed at the maximum transfer rate unless they are gated
by an external request signal or the internal timed request. Transfers to or from a number
of internal I/O addresses are controlled by transfer request signals. These transfer request
signals are connected automatically as a function of the internal I/O address loaded into
the DMA channel. Note that if both the source and the destination are internal I/O, the
source transfer request is used by the DMA channel.
The DMA channels are inherently byte-oriented, so while DMA transfers can be done
from a 16-bit memory, DMA transfers to a 16-bit memory can only be done if the 16-bit
memory is set up to allow byte writes (see Chapter 5 for more information). For memory
to memory transfers, a word transfer will occur if both addresses are aligned, but byte
writes must still be enabled on the destination memory. The Ethernet and Wi-Fi peripherals
are special cases as well — when the 16-bit bus is enabled and the DMA source or desti-
nation address is a network port register, the DMA will attempt to transfer words if the
memory address is aligned.
There are two inputs available for requests linked to external I/O devices. These two external
requests may be assigned to any DMA channel. These requests may also be used by a
channel that has an internal I/O as a destination. In this case, the external request acts as a
“flow control” signal for the DMA transfers because the external request is “ANDed” with
the automatically connected internal request.