Digi Rabbit 5000, User Manual

Page: 258 / 414

258 Rabbit 5000 Microprocessor User’s Manual
The network port receiver uses the received preamble to synchronize to the phase of the
incoming frame, and then waits for the start-frame delimiter. Character assembly begins at
this point, and each byte is transferred to the receive FIFO. However, no interrupt or DMA
request will occur until after the first six bytes of the frame have been received and checked
for an address match. The receiver can receive frames independent of the address (promis-
cuous mode), or it can receive frames with a physical address match, a broadcast address
match, or a multicast address match.
Normal DMA transfers of data begin once an address match occurs, and continue until the
end-frame delimiter is recognized or the line goes idle because of a collision. The network
receiver calculates the CRC across the entire frame in parallel with character assembly,
and reports the result when the end-frame delimiter is recognized. Normally frames with
bad CRC are discarded. The receiver also reports misaligned end-frame delimiters (those
that do not occur on byte boundaries).
The network port implements the NLP receive link integrity test state machine, which
requires link integrity pulses to be detected at certain intervals in the absence of other
network activity. If the network receiver enters the NLP Link Test Fail state because of
missing link-test pulses, this state machine requires seven successive properly timed link
test pulses (or an equal number of FLP bursts) before reporting that the link is again active.
The reset state of this state machine is link-inactive. Note that this is a subtle difference
relative to the normal 10Base-T receive link-integrity state machine, which requires either
link test pulses or carrier sense to make the link active.
The network port implements the auto-negotiation algorithm to determine half-duplex or
full-duplex operation. In addition to its normal automatic operation, this feature can be
disabled or commanded to execute under software control.
The MII interface consists of 20 pins as specified in IEEE 802.3 standard. Two clocks are
provided on the interface, one for transmit and one for receive.
The two A/D converters and single D/A converter are available for customer use when the
Ethernet peripheral is enabled.