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Chapter 22  10/100Base-T Ethernet

279

Enable Network Port Register

(ENPR)

(Address = 0x0430)

Bit(s)

Value

Description

7:6

00

Disable both Network Port B and Network Port C.

01

Enable Network Port B (the 10/100Base-T Ethernet port).

10

Enable Network Port C (the Wi-Fi port). This bit combination is forced whenever 
either SCFG pin is high.

*

11

This bit combination is reserved and must not be used.

5:2

0

These bits are reserved and should be written with zeros.

1:0

00

Network Port C interrupts are disabled.

01

Network Port C interrupts use Interrupt Priority 1.

10

Network Port C interrupts use Interrupt Priority 2.

11

Network Port C interrupts use Interrupt Priority 3.

* Customers wishing to incorporate the Wi-Fi peripheral in their own design should contact Rabbit 

for more information.

Summary of Contents for Rabbit 5000

Page 1: ...Rabbit 5000 Microprocessor User s Manual 019 0168_E...

Page 2: ...ved Digi International Inc reserves the right to make changes and improvements to its products without providing notice Trademarks Rabbit and Dynamic C are registered trademarks of Digi International...

Page 3: ...trum Spreader 25 2 3 3 Clock Doubler 27 2 3 4 32 kHz Clock 30 2 4 Register Descriptions 32 Chapter 3 Reset and Bootstrap 37 3 1 Overview 37 3 1 1 Block Diagram 38 3 1 2 Registers 38 3 2 Dependencies 3...

Page 4: ...y Modes 66 5 3 4 Separate Instruction and Data Space 68 5 3 5 Memory Protection 68 5 3 6 Stack Protection 69 5 4 Register Descriptions 70 Chapter 6 Interrupts 81 6 1 Overview 81 6 2 Operation 82 6 3 I...

Page 5: ...l Port D 105 11 1 Overview 105 11 1 1 Block Diagram 107 11 1 2 Registers 108 11 2 Dependencies 109 11 2 1 I O Pins 109 11 2 2 Clocks 109 11 2 3 Other Registers 109 11 2 4 Interrupts 109 11 3 Operation...

Page 6: ...her Registers 158 15 2 4 Interrupts 158 15 3 Operation 159 15 3 1 Handling Interrupts 159 15 3 2 Example ISR 159 15 4 Register Descriptions 160 Chapter 16 Timer C 163 16 1 Overview 163 16 1 1 Block Di...

Page 7: ...eration 206 19 3 1 Master Setup 207 19 3 2 Slave Setup 207 19 3 3 Master Slave Communication 208 19 3 4 Slave Master Communication 208 19 3 5 Handling Interrupts 208 19 3 6 Example ISR 208 19 3 7 Othe...

Page 8: ...0 22 2 Dependencies 262 22 2 1 I O Pins 262 22 2 2 Clocks 262 22 2 3 Other Registers 262 22 2 4 Interrupts 263 22 3 Operation 263 22 3 1 Setup 264 22 3 2 Transmit 264 22 3 3 Receive 264 22 3 4 Handlin...

Page 9: ...rs 310 26 2 4 Interrupts 310 26 3 Operation 311 26 3 1 Handling Interrupts 311 26 3 2 Example ISR 311 26 4 Register Descriptions 312 Chapter 27 External I O Control 315 27 1 Overview 315 27 1 1 Extern...

Page 10: ...m Mode Violation Interrupt 359 30 3 7 Handling Interrupts in the System User Mode 360 30 4 Register Descriptions 362 Chapter 31 Specifications 369 31 1 DC Characteristics 369 31 2 AC Characteristics 3...

Page 11: ...Table of Contents Appendix B Rabbit 5000 Errata 401 B 1 Errata 401 Index 405...

Page 12: ...Rabbit 5000 Microprocessor User s Manual...

Page 13: ...ith external 16 bit memory devices It also has the ability to support both 8 bit and 16 bit external memory devices The Rabbit 5000 is also the fastest microprocessor from Rabbit now a Digi Internatio...

Page 14: ...writes The Rabbit 5000 requires no external memory driver or interface logic Its 24 bit address bus 8 bit or 16 bit data bus three chip select lines two output enable lines and two write enable lines...

Page 15: ...ental writes by user code and stack over underflows can be trapped by high priority interrupts Security features are also available in the Rabbit 5000 Portions of the new instruction set were introduc...

Page 16: ...D ADDRESS BUS 15 bits Asynch Serial Synch Serial Asynch Bootstrap Synch Bootstrap Serial Port A Asynch Serial IrDA Serial Ports B C D Asynch Serial IrDA Asynch Serial Synch Serial Serial Ports E F Asy...

Page 17: ...z 1 8 V 3 3 V Wi Fi and Ethernet diabled Operating Temp 40 C to 85 C Maximum Clock Speed 100 MHz Digital I O 48 arranged in six 8 bit ports 19 Network Interfaces 10 100Base T 802 11b g Wi Fi 802 11b g...

Page 18: ...3 V Wi Fi and Ethernet disabled 0 35 mA MHz 3 3 V 2 mA MHz 3 3 V 4 mA MHz 5 V Number of Package Pins 289 196 128 128 100 Size of Package LQFP PQFP Spacing Between Package Pins N A 16 16 1 5 mm 0 4mm 1...

Page 19: ...Support for IrDA Communication 6 6 6 None Serial Ports with Support for SDLC HDLC IrDA Communication 2 2 2 None Maximum Asynchronous Baud Rate Clock Speed 8 Clock Speed 8 Clock Speed 8 Clock Speed 32...

Page 20: ...20 Rabbit 5000 Microprocessor User s Manual...

Page 21: ...from the Rabbit 5000 The main clock can be doubled or divided by 2 4 6 or 8 to reduce EMI and power consumption The 32 kHz clock which can be divided by 2 4 8 or 16 can be used instead of the main clo...

Page 22: ...000A W 00000000 Global Clock Modulation 1 Register GCM1R 0x000B W 00000000 Global Clock Double Register GCDR 0x000F R W 00000000 Wi Fi Clock GCSR CPU Clock Peripheral Clock GOCR Divide by 2 CLK Pin Di...

Page 23: ...an external main oscillator when the 32 kHz mode with main oscillator disabled is selected and will output high for all other clock modes The 32 kHz clock input is on the CLK32K pin There is an inter...

Page 24: ...PWM at their desired values When the 32 kHz clock is enabled in GCSR it can be further divided by 2 4 6 or 8 to generate even lower frequencies by enabling those modes in bits 0 2 of GPSCR See Table...

Page 25: ...le differently the maximum cycle shortening at 1 8 V and 25 C is shown in Table 2 2 below Table 2 2 Spectrum Spreader Settings 0 50 MHz 50 MHz GCM0R Value Description Max Cycle Shortening Normal 0x40...

Page 26: ...cific manner with proper time delays GCM0R is only read by the spectrum spreader at the moment when the spectrum spreader is enabled by storing 0x080 in GCM1R If GCM1R is cleared when disabling the sp...

Page 27: ...e clock doubler uses an on chip delay circuit that must be programmed by the user at startup if there is a need to double the clock Table 2 3 lists the recommended delays in GCDR for various oscillato...

Page 28: ...ated by xor ing the delayed and inverted clock with itself If the original clock does not have a 50 50 duty cycle then alternate clocks will have a slightly different length Since the duty cycle of th...

Page 29: ...n the falling edge of the clock are the memory and I O write pulses and the early option memory output enable See Chapter 5 for more information on the early output enable and write enable options The...

Page 30: ...has a very high imped ance making it susceptible to noise moisture and environmental contaminants It is strongly recommended to conformally coat this circuit to limit the effects of humidity and dust...

Page 31: ...rt a time as possible when an ultra sleepy mode is enabled see Chapter 29 for more details on reducing power consumption When the 32 kHz clock is enabled the periodic interrupt is disabled automatical...

Page 32: ...ock from the main clock 010 Processor clock from the main clock Peripheral clock from the main clock 011 Processor clock from the main clock divided by 2 Peripheral clock from the main clock divided b...

Page 33: ...er in 2 ns steps from 0 ns to 52 ns 11 This bit combination is reserved and must not be used 5 0 These bits are reserved and should be written with zeros Global Clock Modulator 1 Register GCM1R Addres...

Page 34: ...time 00100 9 ns nominal low time 00101 10 ns nominal low time 00110 11 ns nominal low time 00111 12 ns nominal low time 01000 13 ns nominal low time 01001 14 ns nominal low time 01010 15 ns nominal lo...

Page 35: ...ode byte fetch 01 STATUS pin is active low during an interrupt acknowledge 10 STATUS pin is low 11 STATUS pin is high 3 2 00 WDTOUT pin functions normally 01 Enable WDTOUT for test mode Rserved for in...

Page 36: ...36 Rabbit 5000 Microprocessor User s Manual...

Page 37: ...ecks the state of the SMODE and SYSCFG pins Depending on the state of the SMODE pins it either begins normal operation by fetching instruction bytes from memory bank zero which is mapped to either CS0...

Page 38: ...et Slave Port Control Register SPCR 0x0024 R W 0xx00000 Reset Delay RESET Reset CPU Clock Rabbit 5000 Master Reset Bootstrap Selection SMODE0 Bootstrap SMODE1 Asynch Serial Bootstrap Serial Flash Boot...

Page 39: ...h powers CS1 In this case a pul lup resistor is required on CS1 to keep the RAM deselected during powerdown RESOUT The RESOUT pin which is powered by the backup battery is high during reset and powerd...

Page 40: ...CS1 to keep the RAM deselected during powerdown The RESOUT pin which is powered by the backup battery is high during reset and powerdown as long as VBAT and VBATIO are present but low at all other tim...

Page 41: ...te of a 16 bit address the second byte is the least significant byte of the address and the third byte is the data to be written If the uppermost bit of the address is 1 then the address is assumed to...

Page 42: ...eing accepting triplets at 2400 bps on Serial Port A The baud rate is generated from the 32 kHz clock input so a 32 kHz clock is required for this mode 3 3 2 Serial Flash Bootstrap When the serial fla...

Page 43: ...he Rabbit 5000 will enable the parallel slave port interface on Parallel Ports A and B and will wait for triplets to be sent to that interface See Chapter 19 for more details on the operation of the s...

Page 44: ...port 010 Enable the slave port with SCS from Parallel Port E bit 7 011 Enable the external I O bus Parallel Port A is used for the data bus and Parallel Port B 7 2 is used for the address bus 100 Thi...

Page 45: ...ithin that time Its purpose is to restart the processor when it detects that a program gets stuck or disabled The secondary watchdog timer can time out from 30 5 s up to 7 8 ms and generates a Priorit...

Page 46: ...Basic System Peripherals Periodic Interrupt 488 s 32 kHz Clock Interrupt Request GCSR Interrupt Generation Real Time Clock RTCxR RTCCR Watchdog Timer Secondary Watchdog Timer WDTCR WDTTR WDTCR SWDTR...

Page 47: ...ime Clock Byte 4 Register RTC4R 0x0006 R xxxxxxxx Real Time Clock Byte 5 Register RTC5R 0x0007 R xxxxxxxx Watchdog Timer Control Register WDTCR 0x0008 W 00000000 Watchdog Timer Test Register WDTTR 0x0...

Page 48: ...he BUFEN pin can be active low during external I O cycles active low during data memory cycles or driven high or low The values in the battery backed onchip encryption RAM bytes are cleared if the sig...

Page 49: ...read again Writing to RTC0R latches the current real time clock value into the RTCxR holding regis ters so the following sequence should be used to read the real time clock 1 Write any value to RTC0R...

Page 50: ...the internal interrupt table 2 Write the desired timeout period to SWDTR This also enables the secondary watchdog timer 3 Restart the secondary watchdog timer by either writing the timeout period to S...

Page 51: ...m the main clock 010 Processor clock from the main clock Peripheral clock from the main clock 011 Processor clock from the main clock divided by two Peripheral clock from the main clock divided by two...

Page 52: ...ement write 5 0 0 No effect on the real time clock counter 1 Increment the corresponding byte of the real time clock counter Real Time Clock x Register RTC0R Address 0x0002 RTC1R Address 0x0003 RTC2R...

Page 53: ...ress 0x000C Bit s Value Description 7 0 The time constant for the secondary watchdog timer is stored This time constant will take effect the next time that the secondary watchdog counter counts down t...

Page 54: ...z 11 This bit combination is reserved and should not be used 1 0 00 BUFEN pin is active low during external I O cycles 01 BUFEN pin is active low during data memory accesses 10 BUFEN pin is low 11 BUF...

Page 55: ...stem Management 55 Battery Backed Onchip Encryption RAM VRAM00 Address 0x0600 through through VRAM31 Address 0x061F Bit s Value Description 7 0 General purpose RAM locations Cleared by Intrusion Detec...

Page 56: ...56 Rabbit 5000 Microprocessor User s Manual...

Page 57: ...ait states depending on the settings Both 8 bit and 16 bit page mode devices are also supported In addition the Rabbit 5000 contains 128 KB of internal SRAM that resides on its own chip select signal...

Page 58: ...l space The boundaries between the root and data segments and the data and stack segments can be adjusted in 4 KB blocks as well The XMEM segment is a fixed 8 KB and points to a physical memory addres...

Page 59: ...ement 59 Figure 5 2 Logical and Physical Memory Mapping 64 KB 16 MB LOGICAL ADDRESS MAP PHYSICAL ADDRESS MAP ROOT DATA SEGMENT STACK SEGMENT XPC 000000 FFFFFF 0000 FFFF E000 x000 y000 SEGSIZE REGISTER...

Page 60: ...ments before bank selection physical device occurs These two features allow both code and data to access separate 64 KB logical spaces instead of sharing a single space It is possible to protect memor...

Page 61: ...R 0x0018 R W 00000000 Memory Timing Control Register MTCR 0x0019 R W 00000000 Memory Alternate Control Register MACR 0x001D R W 00000000 Advanced CS0 Control Register ACS0CR 0x0410 R W 00000000 Advanc...

Page 62: ...0 to allow byte reads and writes in 16 bit SRAM devices 5 2 2 Clocks All memory operations are clocked by the processor clock 5 2 3 Other Registers 5 2 4 Interrupts When a write is attempted to a writ...

Page 63: ...wards compatibility to the Rabbit 2000 and 3000 processors these registers map directly to DATASEGL and STACKSEGL but the contents of DATASEGH and STACKSEGH are set to zero Each of these registers pro...

Page 64: ...ting before use If SYSCFG0 is high and SYSCFG1 is low Memory Bank 0 is enabled to use CS3 OE0 and WE0 in 16 bit mode This allows the processor to start operation directly out of the internal SRAM The...

Page 65: ...es slightly longer strobes for slower memories see the timing diagrams in Chapter 31 These options are available in MTCR It is possible to force CS1 to be always active in MMIDR enabling this will cau...

Page 66: ...s so there is an option to select between these two cases in ACSxCR With the default option any byte writes or unaligned word writes to a 16 bit memory will be suppressed i e the WE will not be assert...

Page 67: ...ode As mentioned previously the ACSxCR registers each contain three fields to control the generation of wait states in the advanced bus modes These settings are in addition to the wait state setting i...

Page 68: ...thin the root or data segments the RAMSR will be ignored if it is mapped to the stack segment or XPC window The Rabbit 5000 Designer s Handbook provides further details on the use of the separate inst...

Page 69: ...interrupt occurs when a stack based write occurs within the 16 bytes below the upper limit or within the 16 bytes above the lower limit Note that the writes will still occur even if they are within t...

Page 70: ...k select address MSB inversion for data accesses only This enables the instruction data split 4 0 Normal CS1 operation 1 Force CS1 always active This will not cause any conflicts as long as the memory...

Page 71: ...address offset to use if SEGSIZ 7 4 Addr 15 12 0xE Data Segment Register DATSEG Address 0x0012 Bit s Value Description 7 0 Read The current contents of this register are reported Write Eight LSBs MSBs...

Page 72: ...states for accesses in this bank 5 0 Pass bank select address MSB for accesses in this bank 1 Invert bank select address MSB for accesses in this bank 4 0 Pass bank select address LSB for accesses in...

Page 73: ...ndependent of bank select address 101 For an XPC access use MB1CR independent of bank select address 110 For an XPC access use MB2CR independent of bank select address 111 For an XPC access use MB3CR...

Page 74: ...ed by strapping a pin this bit is forced high 6 This bit is reserved and must not be used 5 4 00 Normal 8 bit operation for CS2 01 Page Mode 8 bit operation for CS2 10 Normal 16 bit operation for CS2...

Page 75: ...de read access 111 Seven extra wait state for reads writes or first Page Mode read access 4 3 00 Zero extra wait states for subsequent Page Mode accesses 01 One extra wait state for subsequent Page Mo...

Page 76: ...r s Manual Write Protection Control Register WPCR Address 0x0440 Bit s Value Description 7 1 These bits are reserved and should be written with zeros 0 0 Write protection in User Mode only 1 Write pro...

Page 77: ...Address 0x0472 WP19R Address 0x0473 WP20R Address 0x0474 WP21R Address 0x0475 WP22R Address 0x0476 WP23R Address 0x0477 WP24R Address 0x0478 WP25R Address 0x0479 WP26R Address 0x047A WP27R Address 0x...

Page 78: ...ect for relative address 0x5000 0x5FFF in WP Segment x 1 Enable 4 KB write protect for relative address 0x5000 0x5FFF in WP Segment x 4 0 Disable 4 KB write protect for relative address 0x4000 0x4FFF...

Page 79: ...BFFF in WP Segment x 1 Enable 4 KB write protect for relative address 0xB000 0xBFFF in WP Segment x 2 0 Disable 4 KB write protect for relative address 0xA000 0xAFFF in WP Segment x 1 Enable 4 KB writ...

Page 80: ...Limit Register STKHLR Address 0x0446 Bit s Value Description 7 0 Upper limit for stack limit checking If a stack operation or stack relative memory access is attempted at an address greater than STKH...

Page 81: ...any attempt to enter Priority 3 will actually be requested as Priority 2 When an interrupt is handled a call is executed to a fixed location in the interrupt vector tables This operation requires 11 c...

Page 82: ...appropriate chapter for more details 6 3 Interrupt Tables Table 6 1 shows the structure of the internal interrupt vector table The first column is the vector address offset within the table The second...

Page 83: ...wn in Table 6 3 Interrupts marked as cleared automatically have their requests cleared when the inter rupt is first handled Table 6 2 External Interrupt Vector Table Structure Offset 0x0000 0x00 Exter...

Page 84: ...CCSR Slave Port Rd Read from SPD0R SPD1R or SPD2R Wr Write to SPD0R SPD1R SPD2R or dummy write to SPSR DMA 7 Cleared automatically DMA 6 Cleared automatically DMA 5 Cleared automatically DMA 4 Cleared...

Page 85: ...upt pin must be present for at least three peripheral clock cycles to be detected In addition the Rabbit 5000 has a minimum latency of 11 clocks to respond to an interrupt so the minimum external inte...

Page 86: ...s are in the EIR at offsets 0x000 and 0x010 They can be set as Priority 1 2 or 3 in the appropriate IxCR 7 4 Operation The following steps must be taken to enable the external interrupts 1 Write the v...

Page 87: ...ter 7 External Interrupts 87 7 4 1 Example ISR A sample interrupt handler is shown below extInt_isr respond to external interrupt here interrupt is automatically cleared by interrupt acknowledge ipres...

Page 88: ...bble interrupt disabled 01 Parallel Port E high nibble interrupt on falling edge 10 Parallel Port E high nibble interrupt on rising edge 11 Parallel Port E high nibble interrupt on both edges 3 2 00 P...

Page 89: ...e SMODE pins have selected the slave port bootstrap mode Parallel Port A will be the slave port data bus until disabled by the processor Parallel Port A can also be used as an external I O data bus to...

Page 90: ...ock 8 2 3 Other Registers 8 2 4 Interrupts There are no interrupts associated with Parallel Port A except when the slave port is being used 8 3 Operation The following steps explain how to set up Para...

Page 91: ...th zero 4 2 000 Disable the slave port Parallel Port A is a byte wide input port 001 Disable the slave port Parallel Port A is a byte wide output port 010 Enable the slave port with SCS from Parallel...

Page 92: ...92 Rabbit 5000 Microprocessor User s Manual...

Page 93: ...ve Read strobe Slave Write strobe and Slave Address inputs The Slave Chip Select can also be programmed to come from a Parallel Port B pin When the external I O bus option is enabled either six or eig...

Page 94: ...Parallel Port B pins associated with those peripherals perform those actions no matter what the settings are in PBDR or PBDDR See the associated peripheral chapters for details on how they use Parall...

Page 95: ...ther setup information Once the port is set up data can be read or written by accessing PBDR The value in PBDR of an output pin will reflect its current output value but any value written to an input...

Page 96: ...ble the slave port with SCS from Parallel Port E bit 7 011 Enable the external I O bus Parallel Port A is used for the data bus and Parallel Port B 7 2 is used for the address bus 100 This bit combina...

Page 97: ...be used as inputs to various on chip peripherals Table 10 1 Parallel Port C Pin Alternate Output Functions Pin Name Alt Out 0 Alt Out 1 Alt Out 2 Alt Out 3 PC7 TXA I7 PWM3 SCLKC PC6 TXA I6 PWM2 TXE PC...

Page 98: ...an output the value it is set to is returned 10 1 1 Block Diagram 10 1 2 Registers Register Name Mnemonic I O Address R W Reset Port C Data Register PCDR 0x0050 R W 00010101 Port C Data Direction Reg...

Page 99: ...10 2 3 Other Registers 10 2 4 Interrupts There are no interrupts associated with Parallel Port C 10 3 Operation The following steps must be taken before using Parallel Port C 1 Select the desired inp...

Page 100: ...e Description 7 6 00 Parallel Port C bit 3 alternate output 0 TXC 01 Parallel Port C bit 3 alternate output 1 I3 10 Parallel Port C bit 3 alternate output 2 TIMER C3 11 Parallel Port C bit 3 alternate...

Page 101: ...Parallel Port C bit 5 alternate output 1 I5 10 Parallel Port C bit 5 alternate output 2 PWM1 11 Parallel Port C bit 5 alternate output 3 RCLKE 1 0 00 Parallel Port C bit 4 alternate output 0 TXB 01 Pa...

Page 102: ...ceive operation simultaneously 5 4 00 Parallel Port C is used for input 01 Parallel Port D is used for input 10 Parallel Port E is used for input 11 Disable the receiver input 3 2 00 Asynchronous mode...

Page 103: ...ort bit 1 for Start condition input 01 Use port bit 3 for Start condition input 10 Use port bit 5 for Start condition input 11 Use port bit 7 for Start condition input 3 2 00 Parallel Port C used for...

Page 104: ...104 Rabbit 5000 Microprocessor User s Manual...

Page 105: ...ts of Timer A1 Timer B1 or Timer B2 can be used for this function with each nibble of the port having a separate select field to control this timing Each bit can either be pro grammed as open drain or...

Page 106: ...ort D Pin Alternate Input Functions Pin Name Input Capture Serial Ports A D Serial Ports E F DMA External Interrupts Quad Decode PD7 RXA RXE PD6 PD5 RXB RCLKE PD4 TCLKE PD3 RXC RXF DREQ1 QRD2A PD2 SCL...

Page 107: ...DCR PDDR PDBxR Data 7 0 External I O Strobes Serial Ports A F Tx Rx Clocks 7 0 7 0 3 0 PWM Output Timer C Output Input Capture 3 0 7 5 3 1 Quadrature Decoder 3 0 7 4 External I O Address 7 6 DMA Reque...

Page 108: ...unction Register PDFR 0x0065 R W xxxxxxxx Port D Drive Control Register PDDCR 0x0066 R W xxxxxxxx Port D Data Direction Register PDDDR 0x0067 R W 00000000 Port D Bit 0 Register PDB0R 0x0068 W xxxxxxxx...

Page 109: ...Port D 11 2 2 Clocks All outputs on Parallel Port D are clocked by the peripheral clock unless changed in PDCR where the option of updating the Parallel Port D pins can be synchronized to the output...

Page 110: ...uts via PDDCR 3 If an alternative peripheral output function is desired for a pin select it via PDALR or PDAHR and then enable it via PDFR Refer to the appropriate peripheral chapter for further use o...

Page 111: ...arallel Port D bit 3 alternate output 1 I3 10 Parallel Port D bit 3 alternate output 2 TIMER C3 11 Parallel Port D bit 3 alternate output 3 SCLKD 5 4 00 Parallel Port D bit 2 alternate output 0 SCLKC...

Page 112: ...ort D bit 4 alternate output 0 TXB 01 Parallel Port D bit 4 alternate output 1 I4 10 Parallel Port D bit 4 alternate output 2 PWM0 11 Parallel Port D bit 4 alternate output 3 TCLKE Parallel Port D Con...

Page 113: ...Address 0x0067 Bit s Value Description 7 0 0 The corresponding port bit is an input 1 The corresponding port bit is an output Parallel Port D Bit 0 Register PDB0R Address 0x0068 Bit s Value Descripti...

Page 114: ...his bit The port buffer will be transferred to the port output register on the next rising edge of the port transfer clock Parallel Port D Bit 4 Register PDB4R Address 0x006C Bit s Value Description 7...

Page 115: ...t The port buffer will be transferred to the port output register on the next rising edge of the port transfer clock Parallel Port D Bit 7 Register PDB7R Address 0x006F Bit s Value Description 6 0 The...

Page 116: ...ceive operation simultaneously 5 4 00 Parallel Port C is used for input 01 Parallel Port D is used for input 10 Parallel Port E is used for input 11 Disable the receiver input 3 2 00 Asynchronous mode...

Page 117: ...ort bit 1 for Start condition input 01 Use port bit 3 for Start condition input 10 Use port bit 5 for Start condition input 11 Use port bit 7 for Start condition input 3 2 00 Parallel Port C used for...

Page 118: ...counters both channels 1 Ten bit quadrature decoder counters both channels 4 This bit is reserved and should be written as zero 3 2 00 Disable Quadrature Decoder 1 inputs Writing a new value to these...

Page 119: ...led 01 Parallel Port E high nibble interrupt on falling edge 10 Parallel Port E high nibble interrupt on rising edge 11 Parallel Port E high nibble interrupt on both edges 3 2 00 Parallel Port E low n...

Page 120: ...sfer per request 01 External DMA Request 0 rising edge triggered One transfer per request 10 External DMA Request 0 active low Transfers continue while low 11 External DMA Request 0 active high Transf...

Page 121: ...request 01 External DMA Request 1 rising edge triggered One transfer per request 10 External DMA Request 1 active low Transfers continue while low 11 External DMA Request 1 active high Transfers conti...

Page 122: ...122 Rabbit 4000 Microprocessor User s Manual...

Page 123: ...le of the port having a separate select field to control this timing Each bit can either be pro grammed as open drain or driven high and low Because of the buffered nature of Parallel Port E using a r...

Page 124: ...Input Functions Pin Name Input Capture I O Hand shake Serial Ports A D Serial Ports E F DMA External Interrupts Quad Decode PE7 RXA RXE DREQ1 PE6 DREQ0 PE5 RXB RCLKE INT1 PE4 TCLKE INT0 PE3 RXC RXF D...

Page 125: ...R PEDDR PEDCR PEDR PEBxR Data 7 0 7 0 Serial Ports C F Tx Rx Clocks 7 0 4 0 PWM Output Timer C Output Input Capture 7 0 7 5 3 1 Quadrature Decoder 3 0 7 4 A0 A 23 20 External I O Strobes and Handshake...

Page 126: ...are clocked by the peripheral clock unless changed in PECR where the option of updating the Parallel Port E pins can be synchronized to the output of Timer A1 Timer B1 or Timer B2 Register Name Mnemo...

Page 127: ...use of that pin Once the port is set up data can be read or written by accessing PEDR Read PEDR to learn the current state of a Parallel Port E pin any value written to an input pin will not appear o...

Page 128: ...I3 01 Parallel Port E bit 3 alternate output 1 A23 10 Parallel Port E bit 3 alternate output 2 TIMER C3 11 Parallel Port E bit 3 alternate output 3 SCLKD 5 4 00 Parallel Port E bit 2 alternate output...

Page 129: ...rt E bit 5 alternate output 3 RCLKE 1 0 00 Parallel Port E bit 4 alternate output 0 I4 01 Parallel Port E bit 4 alternate output 1 A0 10 Parallel Port E bit 4 alternate output 2 PWM0 11 Parallel Port...

Page 130: ...ster PEDDR Address 0x0077 Bit s Value Description 7 0 0 The corresponding port bit is an input 1 The corresponding port bit is an output Parallel Port E Bit 0 Register PEB0R Address 0x0078 Bit s Value...

Page 131: ...bit The port buffer will be transferred to the port output register on the next rising edge of the peripheral clock Parallel Port E Bit 4 Register PEB4R Address 0x007C Bit s Value Description 7 5 3 0...

Page 132: ...of this bit The port buffer will be transferred to the port output register on the next rising edge of the peripheral clock Parallel Port E Bit 7 Register PEB7R Address 0x007F Bit s Value Description...

Page 133: ...peration simultaneously 5 4 00 Parallel Port C is used for input 01 Parallel Port D is used for input 10 Parallel Port E is used for input 11 Disable the receiver input 3 2 00 Asynchronous mode with 8...

Page 134: ...0 Use port bit 1 for Start condition input 01 Use port bit 3 for Start condition input 10 Use port bit 5 for Start condition input 11 Use port bit 7 for Start condition input 3 2 00 Parallel Port C us...

Page 135: ...rs both channels 1 Ten bit quadrature decoder counters both channels 4 This bit is reserved and should be written as zero 3 2 00 Disable Quadrature Decoder 1 inputs Writing a new value to these bits w...

Page 136: ...t disabled 01 Parallel Port E high nibble interrupt on falling edge 10 Parallel Port E high nibble interrupt on rising edge 11 Parallel Port E high nibble interrupt on both edges 3 2 00 Parallel Port...

Page 137: ...r request 01 External DMA Request 0 rising edge triggered One transfer per request 10 External DMA Request 0 active low Transfers continue while low 11 External DMA Request 0 active high Transfers con...

Page 138: ...te per request 01 External DMA Request 1 rising edge triggered One transfer per request 10 External DMA Request 1 active low Transfers continue while low 11 External DMA Request 1 active high Transfer...

Page 139: ...e slave port with SCS from Parallel Port E bit 7 011 Enable the external I O bus Parallel Port A is used for the data bus and Parallel Port B 7 2 is used for the address bus 100 This bit combination i...

Page 140: ...I O transaction held until signal goes low 3 This bit is reserved and should be written with zero 2 0 000 Use Parallel Port E bit 0 for I O handshake 001 Use Parallel Port E bit 1 for I O handshake 0...

Page 141: ...andshake for I O Bank 2 1 0 Disable I O handshake for I O Bank 1 1 Enable I O handshake for I O Bank 1 0 0 Disable I O handshake for I O Bank 0 1 Enable I O handshake for I O Bank 0 I O Handshake Time...

Page 142: ...142 Rabbit 5000 Microprocessor User s Manual...

Page 143: ...t pins Each bit can either be programmed as open drain or driven high and low Parallel Port H acts as the upper byte of the data bus when the 16 bit mode is enabled all other Parallel Port H functiona...

Page 144: ...00000 Port H Alternate High Register PHAHR 0x0033 R W 00000000 Port H Function Register PHFR 0x0035 R W 00000000 Port H Drive Control Register PHDCR 0x0036 R W 00000000 Port H Data Direction Register...

Page 145: ...13 2 4 Interrupts There are no interrupts associated with Parallel Port H 13 3 Operation The following steps must be taken before using Parallel Port H 1 Select the desired input output direction for...

Page 146: ...bit 3 alternate output 1 I3 10 Parallel Port H bit 3 alternate output 2 TIMER C3 11 Parallel Port H bit 3 alternate output 3 SCLKD 5 4 00 This value is reserved and must not be used 01 Parallel Port H...

Page 147: ...arallel Port H bit 5 alternate output 1 I5 10 Parallel Port H bit 5 alternate output 2 PWM1 11 Parallel Port H bit 5 alternate output 3 RCLKE 1 0 00 This value is reserved and must not be used 01 Para...

Page 148: ...6 bit operation for CS3 Use MBxCR for wait states When stand alone operation is selected by strapping a pin this bit is forced high 6 This bit is reserved and must not be used 5 4 00 Normal 8 bit oper...

Page 149: ...he negative edge of these pulses When the counter reaches zero the reload register is loaded into the counter on the next input pulse instead of a count being performed The terminal count condition fo...

Page 150: ...e If a bit is on and the corresponding interrupt is enabled an interrupt will occur when priorities allow However a separate interrupt is not guaranteed for each bit with an enabled interrupt If the b...

Page 151: ...erclk 2 Timer A2 Timer A7 Parallel Ports D E Control Timer B Timer C Input Capture PWM Quadrature Decoder Timer A8 Timer A9 Timer A10 Serial Ports A F Interrupt Generation Output TACR TACSR TATxR Inte...

Page 152: ...tatus Register TACSR 0x00A0 R W 00000000 Timer A Prescale Register TAPR 0x00A1 R W xxxxxxx1 Timer A Time Constant 1 Register TAT1R 0x00A3 R W xxxxxxxx Timer A Control Register TACR 0x00A4 R W 00000000...

Page 153: ...alue to TATxR for all timers that will be used 4 Enable Timer A by writing a 1 to bit 0 of TACSR 14 3 1 Handling Interrupts The following steps explain how an interrupt is set up and used 1 Write the...

Page 154: ...bits are cleared by the read of this register as is the Timer A interrupt 7 1 0 The corresponding Timer A interrupt is disabled Write only 1 The corresponding Timer A interrupt is enabled 0 0 The clo...

Page 155: ...r A1 2 0 Timer A2 clocked by the main Timer A clock 1 Timer A2 clocked by the output of Timer A1 1 0 00 Timer A interrupts are disabled 01 Timer A interrupt use Interrupt Priority 1 10 Timer A interru...

Page 156: ...or clock from the main clock divided by two Peripheral clock from the main clock divided by two 100 Processor clock from the 32 kHz clock optionally divided via GPSCR Peripheral clock from the 32 kHz...

Page 157: ...B can clock the outputs on Parallel Ports D and E The compare value comes from either the match register or the value internally generated via the step register When using the match register a new ma...

Page 158: ...is cleared when TBCSR is read Register Name Mnemonic I O Address R W Reset Timer B Control Status Register TBCSR 0x00B0 R W xxxx0000 Timer B Control Register TBCR 0x00B1 R W xx000000 Timer B MSB 1 Reg...

Page 159: ...et up and used 1 Write the vector to the interrupt service routine to the internal interrupt table 2 Configure TBCSR to select which match register will generate an interrupt 3 Configure TBCR to selec...

Page 160: ...er B is disabled 1 The clock input for Timer B is enabled Timer B Control Register TBCR Address 0x00B1 Bit s Value Description 7 6 These bits are reserved and should be written with zero 5 0 Normal Ti...

Page 161: ...detects a match Timer B Step LSB x Register TBSL1R Address 0x00BA TBSL2R Address 0x00BC Bit s Value Description 7 0 Eight LSBs of the step size for the Timer B comparator The new compare value will b...

Page 162: ...r clock from the main clock Peripheral clock from the main clock 011 Processor clock from the main clock divided by two Peripheral clock from the main clock divided by two 100 Processor clock from the...

Page 163: ...counter is reloaded with zeros allowing the con trol registers to be reloaded at any time during the count cycle Timer C can generate an interrupt when the count limit value is reached A separate Tim...

Page 164: ...ssor User s Manual 16 1 1 Block Diagram Timer C TCCR perclk 2 perclk 16 Timer A1 Interrupt Generation Interrupt Request Up Counter Divider Registers Timer Cx RESET set x Register reset x Register Set...

Page 165: ...er TCS1LR 0x050C R W xxxxxxxx Timer C Set 1 High Register TCS1HR 0x050D R W xxxxxxxx Timer C Reset 1 Low Register TCR1LR 0x050E R W xxxxxxxx Timer C Reset 1 High Register TCR1HR 0x050F R W xxxxxxxx Ti...

Page 166: ...eripheral clock divided by 2 by the peripheral clock divided by 16 or by the output of Timer A1 as selected in TCCR 16 2 3 Other Registers 16 2 4 Interrupts A Timer C interrupt is enabled in TCCR and...

Page 167: ...TCBPR 5 Enable the desired output pins for Timer C by writing to the appropriate parallel port function and alternate output registers 6 Enable Timer C by writing a 1 to bit 0 of TCCSR 16 3 1 Handling...

Page 168: ...These bits are reserved and should be written with zero 3 2 00 Timer C clocked by the peripheral clock divided by 2 01 Timer C clocked by the output of Timer A1 10 Timer C clocked by the peripheral cl...

Page 169: ...x Timer C Reset x Low Register TCR0LR Address 0x050A TCR1LR Address 0x050E TCR2LR Address 0x051A TCR3LR Address 0x051E Bit s Value Description 7 0 Eight LSBs of the match value to reset Timer C Output...

Page 170: ...in clock 010 Processor clock from the main clock Peripheral clock from the main clock 011 Processor clock from the main clock divided by two Peripheral clock from the main clock divided by two 100 Pro...

Page 171: ...uffering a byte may be read while another byte is being received or the next byte to be transmitted can be loaded while the current byte is still being transferred out The status of each serial port i...

Page 172: ...cks can be generated from the appropriate 8 bit timer from Timer A shown in Table 17 1 or from a dedicated n 1 15 bit divider In either case the resulting bit data rate in the asynchronous mode is 1 8...

Page 173: ...e break or charac ter assembly can be inhibited to reduce the interrupt overhead 17 1 1 Block Diagram Serial Ports A D Peripheral Clock Serial Port Control 15 bit Divider Timer Ax Output Tx Pins SxDHR...

Page 174: ...ister SBER 0x00D5 R W 00000000 Serial Port B Divider Low Register SBDLR 0x00D6 R W xxxxxxxx Serial Port B Divider High Register SBDHR 0x00D7 R W 0xxxxxxx Serial Port C Data Register SCDR 0x00E0 R W xx...

Page 175: ...PD2 or PE2 NOTE When Serial Port C is used as a clocked serial port the parallel port pin used to transmit the serial clock will not be available for other use Serial Port D can transmit on parallel p...

Page 176: ...2 3 and 7 of the Serial Port Status Registers The serial port interrupt vectors are located in the IIR as follows Serial Port A at offset 0x0C0 Serial Port B at offset 0x0D0 Serial Port C at offset 0x...

Page 177: ...dditional options by writing to SxER parity RZI encoding clock polarity and behavior during break 5 Write the desired divider value to TATxR for the appropriate serial port or else write a divider val...

Page 178: ...o SxER clock polarity bit order and clock source if external 5 Write the desired divider value to TATxR for the appropriate serial port or else write a divider to the dedicated 15 bit divider in SxDLR...

Page 179: ...read byte and clear interrupt do something with received byte here ld a 0x4D set bits 6 7 to 01 the other bits should represent the desired SBCR setup Parallel Port C internal clock Interrupt Priority...

Page 180: ...n the clocked serial mode automatically causes the receiver to start a byte receive operation eliminating the need for software to issue the start receive command Write Loads the transmit buffer with...

Page 181: ...eive buffer was not overrun 1 The receive buffer was overrun This bit is cleared by reading the receive buffer 4 0 The byte in the receive buffer has no parity error or was not checked for parity 1 Th...

Page 182: ...er was overrun This bit is cleared by reading the receive buffer 4 0 This bit is always zero in the clocked serial mode 3 0 The transmit buffer is empty 1 The transmit buffer is not empty The serial p...

Page 183: ...peration simultaneously 5 4 00 Parallel Port C is used for input 01 Parallel Port D is used for input 10 Parallel Port E is used for input 11 Disable the receiver input 3 2 00 Asynchronous mode with 8...

Page 184: ...nd checking with space always zero parity 111 Enable parity generation and checking with mark always one parity 4 0 Normal asynchronous data encoding 1 Enable RZI coding 3 16 bit cell IrDA compliant 3...

Page 185: ...l clock 11 Inverted clocked serial clock polarity inactive high Internal clock only 3 0 Normal bit order LSB first for transmit and receive 1 Reverse bit order MSB first for transmit and receive 2 0 S...

Page 186: ...0x00F7 Bit s Value Description 7 0 Disable the serial port divider and use the output of Timer A to clock the serial port 1 Enable the serial port divider and use its output to clock the serial port T...

Page 187: ...as over run a parity error was received the transmit buffer is empty or busy sending a byte and the state of the ninth data bit whether it is an address bit or a stop bit Serial Ports E and F support...

Page 188: ...ta rate clock is supported In this case the maximum data rate is 1 6 of the peripheral clock rate The receive clock is gener ated from the transitions in the data stream via a digital phase locked loo...

Page 189: ...EER 0x00CD R W 00000000 Serial Port E Divider Low Register SEDLR 0x00CE R W xxxxxxxx Serial Port E Divider High Register SEDHR 0x00CF R W 0xxxxxxx Serial Port F Data Register SFDR 0x00D8 R W xxxxxxxx...

Page 190: ...e the receive serial clock is either trans mitted or received on PC1 PD1 or PE1 The transmit and receive clocks can also be transmitted on PH5 or PH1 if internal clock mode is enabled 18 2 2 Clocks Th...

Page 191: ...buffer is empty These occurrences correspond to bits 2 3 and 7 of the Serial Port Status Registers In the HDLC mode interrupts are also generated by the reception of an end of frame with abort valid C...

Page 192: ...te serial port or else write a divider to the dedicated 15 bit divider in SxDLR and SxDHR If the dedicated divider is to be used write a 1 to the most significant bit of SxDHR to enable it In either c...

Page 193: ...o SEAR or SELR instead ioi ld SEDR a load next byte into buffer and clear interrupt done pop af ipres ret 18 3 3 More on Clock Synchronization and Data Encoding The transmitter is not capable of sendi...

Page 194: ...transitions on the receive data stream to adjust its count The DPLL adjusts the count so that the DPLL output will be properly placed in the bit cells to sample the receive data To work properly then...

Page 195: ...are present in the receive data stream Two consecu tive missed transitions causes the DPLL to halt operation and wait for the next available transition This mode of operation is necessary because it...

Page 196: ...lock transition at the center of every bit cell and optional data transitions occur at the bit cell boundaries The DPLL only uses the clock transitions to track the bit cell boundaries by ignoring all...

Page 197: ...Address 0x00C8 SFDR Address 0x00D8 Bit s Value Description 7 0 Read Returns the contents of the receive buffer Write Loads the transmit buffer with a data byte for transmission Serial Port x Address...

Page 198: ...as not overrun 1 The receive buffer was overrun This bit is cleared by reading the receive buffer 4 0 The byte in the receive buffer has no parity error or was not checked for parity 1 The byte in the...

Page 199: ...uffer is not empty The serial port will request an interrupt when the transmitter takes a byte from the transmit buffer unless the byte is marked as the last in the frame Transmit interrupts are clear...

Page 200: ...eceiver data input Clocks from Parallel Port E 3 2 00 Asynchronous mode with 8 bits per character 01 Asynchronous mode with 7 bits per character In this mode the most significant bit of a byte is igno...

Page 201: ...ays zero parity 111 Enable parity generation and checking with mark always one parity 4 0 Normal asynchronous data encoding 1 Enable RZI coding 3 16 bit cell IrDA compliant 3 0 Normal break operation...

Page 202: ...nsmit flag on underrun 1 Transmit abort on underrun 1 0 Separate HDLC external receive and transmit clocks 1 Combined HDLC external and transmit clock from transmit clock pin 0 This bit is ignored in...

Page 203: ...nput or data output register to indicate the empty or full status of the data register Data registers are marked full when written by the source side of the interface and are marked empty when read by...

Page 204: ...c I O Address R W Reset Slave Port Data 0 Register SPD0R 0x0020 R W xxxxxxxx Slave Port Data 1 Register SPD1R 0x0021 R W xxxxxxxx Slave Port Data 2 Register SPD2R 0x0022 R W xxxxxxxx Slave Port Status...

Page 205: ...slave device whenever the master writes to SPD0R The SLVATTN pin is asserted whenever the slave device writes to SPD0R Either if these conditions is cleared when either the master or slave reads or w...

Page 206: ...lave port connection between a Rabbit processor as the master and two slaves Figure 19 1 Master Slave Port Connections MASTER Rabbit First SLAVE Rabbit Second SLAVE Rabbit D0 D7 IORD IOWR A0 A1 CLK PE...

Page 207: ...ange on SLVATTN it reads the slave port data registers 19 3 1 Master Setup 1 Enable the I O strobes on PD6 and PD7 by writing to the appropriate Parallel Port D pin and external I O registers 2 Enable...

Page 208: ...t is writing multiple bytes SPD0R should be written last which enables the SLVATTN line 2 The master receives an external interrupt from the SLVATTN line and reads the data out of the slave port data...

Page 209: ...guration is useful when fewer signals are desired or the master device has no external interrupts available If polling is to be used it is important to note that not all bits in the status register ma...

Page 210: ...master reads writes the slave port registers Figure 19 2 Slave Port R W Timing Diagram SCS SD 7 0 SRD Slave Port Read Cycle Slave Port Write Cycle SWR SA1 SA0 Tsu SCS Tsu SA Th SA Th SCS Tw SRD Ten S...

Page 211: ...CS SCS Hold Time 0 Tsu SA SA Setup Time 5 Th SA SA Hold Time 0 Tw SRD SRD Low Pulse Width 40 Ten SRD SRD to SD Enable Time 0 Ta SRD SRD to SD Access Time 30 Tdis SRD SRD to SD Disable Time 15 Tsu SRW...

Page 212: ...s Value Description 7 0 Processor wrote to SPSR 1 Master wrote to Data Register 0 6 0 Slave port read byte 2 is empty 1 Slave port read byte 2 is full 5 0 Slave port read byte 1 is empty 1 Slave port...

Page 213: ...lave port with SCS from Parallel Port E bit 7 011 Enable the external I O bus Parallel Port A is used for the data bus and Parallel Port B 7 2 is used for the address bus 100 This bit combination is r...

Page 214: ...214 Rabbit 5000 Microprocessor User s Manual...

Page 215: ...onversion rates depend on the clock sources used each analog component can accept a clock from an external I O pin or divide the peripheral clock by a value between 2 and 256 Table 20 1 Analog Compone...

Page 216: ...y Differential DNL Integral INL 0 5 LSB typ 1 LSB typ Offset Error I to Q Offset Mismatch 2 of full scale 1 of full scale Gain Error I to Q Gain Mismatch 5 of full scale 1 of full scale Channel Isolat...

Page 217: ...g Current Active Standby 35 A 1 8 V 62 A 3 3 V 1 A 1 8 V 3 3 V Transition Time Standby to active 15 s Nonlinearity Differential DNL Integral INL 1 LSB typ 2 LSB max Offset Error 1 5 to 2 5 LSB Gain Er...

Page 218: ...Peripheral Clock PD4 Component 0 Fast A D Converter VINIP VININ VINQP VINQN VINIP VININ VINQP VINQN A0QLR A0QMR A0ILR A0IMR A0CR Fast D A Converter Clock Select PD5 Component 1 Fast D A Converter A1I...

Page 219: ...he peripheral clock divided by 2 4 8 16 32 64 128 or 256 or by a clock input on PD4 PD5 or PD6 depending on the com ponent Exercise care when selecting the clock to keep the data rate below the maximu...

Page 220: ...ta to the A1IxR and A1QxR registers Writing the least significant bit registers first will hold the conversion output until the most significant bit register is written 3 For faster update an 8 bit va...

Page 221: ...st A D Converter Circuit Figure 20 2 Sample Fast D A Converter Circuit 1 8 V 100 nF 2 2 F VDDI VSSI 100 nF 2 2 F 3 3 V AVDDI AGNDI AGNDREF 100 nF VDD33 A33GNDI 100 nF AVDDI AGNDI 100 nF 2 2 F VREFP VR...

Page 222: ...222 Rabbit 5000 Microprocessor User s Manual Figure 20 3 Sample Slow A D Converter Circuit 3 3 V 100 nF 2 2 F VDD33 A33GND Ferrite Bead VIN8 SLOW ADC ANALOG INTPUT...

Page 223: ...ading this register locks the value in the corresponding MSB register to guarantee that the full 10 bits are valid Write Writes to these bits are ignored 5 0 These bits are ignored and will always ret...

Page 224: ...st A D converter I channel 1 Enable fast A D converter I channel 1 0 00 Fast A D converter powered down 01 Fast A D converter in sleep mode 10 Fast A D converter active outputting unsigned binary 11 F...

Page 225: ...n 7 0 Use peripheral clock as fast D A converter clock source 1 Use Parallel Port PD5 as fast D A converter clock source 6 4 000 Clock divided by 2 001 Clock divided by 4 010 Clock divided by 8 011 Cl...

Page 226: ...s register locks the value in the corresponding MSB register to guarantee that the full 10 bits are valid Write Writes to this register are ignored 5 0 These bits are ignored and will always return ze...

Page 227: ...2 001 Clock divided by 4 010 Clock divided by 8 011 Clock divided by 16 100 Clock divided by 32 101 Clock divided by 64 110 Clock divided by 128 111 Clock divided by 256 3 0 Conversion not complete R...

Page 228: ...228 Rabbit 5000 Microprocessor User s Manual...

Page 229: ...addresses are controlled by transfer request signals These transfer request signals are connected automatically as a function of the internal I O address loaded into the DMA channel Note that if both...

Page 230: ...er descriptor in memory consists of either 12 or 16 consecutive bytes organized as shown in Table 21 1 The DMA channel uses the information in the control byte to deter mine the length of the buffer d...

Page 231: ...rs can occur This allows interrupt services routines or other critical code to run with a guarantee that there will be no DMA activity during execution Note that a simultaneous interrupt request and D...

Page 232: ...DMCR External Requests PD 3 2 PE 3 2 PE 7 6 Timed Request Counter DTRCR DTRDLR DTRDHR DMA Channel y Master Control Channel n State Machine DMCSR DMALR DMHR DMCR DMTCR Buffer Complete Counter Buffer Un...

Page 233: ...0 Register DyBU0R 0x01yA R 00000000 DMA y Buffer Unused 15 8 Register DyBU1R 0x01yB R 00000000 DMA y Initial Address 7 0 Register DyIA0R 0x01yC R W xxxxxxxx DMA y Initial Address 15 8 Register DyIA1R...

Page 234: ...for all operations If the timed request option is enabled then the 16 bit timed request counter will be clocked by the peripheral clock and will provide a DMA request each time it counts down to zero...

Page 235: ...er values by writing to DMCSR The following steps explain how to set up a DMA channel 1 Select the DMA transfer and interrupt priorities by writing to DMCR 2 Select the DMA channel priority maximum by...

Page 236: ...andler is shown below dma_isr push af do something with the data in the current buffer the interrupt request is automatically cleared pop af ipres ret 21 3 3 DMA Priority with the Processor Since the...

Page 237: ...of overhead This overhead comes about because the DMA actually uses part of the processor to perform the data transfers and consists of one instruction fetch time plus three clock cycles The byte fetc...

Page 238: ...er each byte transferred and if a higher priority channel has a pending request the current transfer will be terminated and the new channel transfer will start The other option is to rotate after ever...

Page 239: ...generate interrupts The advantage of the buffer array is that its descriptors require less memory than a full 16 byte descriptor The simplest version of the buffer array is a double buffer which is f...

Page 240: ...and the descriptors are not necessarily adjacent in memory The advantage of this mode is the ability to spread descriptors Buffer Descriptor 12 bytes Initial Address Linked List Interrupt Buffer Desc...

Page 241: ...hile the other buffer is being loaded 21 3 5 5 Linked Array The linked array is simply a linked list of buffer arrays where the last buffer in each array is linked to the first buffer in the next arra...

Page 242: ...on to automatically send and receive packets via DMA only requiring direct handling of a packet when an error occurs 21 3 6 2 DMA with Ethernet The Ethernet network peripheral also receives special ha...

Page 243: ...nly 1 The corresponding DMA channel is enabled and active These bits are set by the start command and remain set until the completion of the last buffer DMA Master Auto Load Register DMALR Address 0x0...

Page 244: ...This feature is intended only for testing because the DMA automatically resets the counter to all ones when fetching from the initial address The counter is incremented whenever the DMA fetches a new...

Page 245: ...after the current channel request is serviced 5 3 000 Maximum one byte per burst 001 Maximum two bytes per burst 010 Maximum three bytes per burst 011 Maximum four bytes per burst 100 Maximum eight b...

Page 246: ...sfer per request 01 External DMA Request 0 rising edge triggered One transfer per request 10 External DMA Request 0 active low Transfers continue while low 11 External DMA Request 0 active high Transf...

Page 247: ...request 01 External DMA Request 1 rising edge triggered One transfer per request 10 External DMA Request 1 active low Transfers continue while low 11 External DMA Request 1 active high Transfers cont...

Page 248: ...be used 2 0 000 Timed DMA request supplied to DMA Channel 0 001 Timed DMA request supplied to DMA Channel 1 010 Timed DMA request supplied to DMA Channel 2 011 Timed DMA request supplied to DMA Chann...

Page 249: ...be used in the compare to generate the termination condition A zero in a bit position disables the corresponding bit from contributing to the termination condition A value of all zeros in this registe...

Page 250: ...R Address 0x016C D7IA0R Address 0x017C Bit s Value Description 7 0 Bits 7 0 of the initial address are stored in this register DMA y Initial Addr 15 8 Register D0IA1R Address 0x010D D1IA1R Address 0x0...

Page 251: ...F0 Bit s Value Description 7 4 These bits are reserved and will always be read as zeros 3 0 Auto connect source DMA request 1 Disconnect source DMA request full buffer transfer 2 0 Normal source addre...

Page 252: ...s long 5 0 No special treatment for last byte 1 Internal Source status byte written to initial buffer descriptor before last data Internal Destination Last byte written to offset address for frame ter...

Page 253: ...uffer length value are stored in this register The DMA does a transfer followed by a decrement of this register so an initial value of 0x0000 will result in a 65536 byte transfer DMA y Length 15 8 Reg...

Page 254: ...ster D0SA1R Address 0x0185 D1SA1R Address 0x0195 D2SA1R Address 0x01A5 D3SA1R Address 0x01B5 D4SA1R Address 0x01C5 D5SA1R Address 0x01D5 D6SA1R Address 0x01E5 D7SA1R Address 0x01F5 Bit s Value Descrip...

Page 255: ...1R Address 0x0189 D1DA1R Address 0x0199 D2DA1R Address 0x01A9 D3DA1R Address 0x01B9 D4DA1R Address 0x01C9 D5DA1R Address 0x01D9 D6DA1R Address 0x01E9 D7DA1R Address 0x01F9 Bit s Value Description 7 0...

Page 256: ...ster D0LA1R Address 0x018D D1LA1R Address 0x019D D2LA1R Address 0x01AD D3LA1R Address 0x01BD D4LA1R Address 0x01CD D5LA1R Address 0x01DD D6LA1R Address 0x01ED D7LA1R Address 0x01FD Bit s Value Descrip...

Page 257: ...of status will be transferred to memory The DMA must be programmed to close a buffer on end of frame as the network port marks the last byte of status this way The Network Port B transmitter uses int...

Page 258: ...miters those that do not occur on byte boundaries The network port implements the NLP receive link integrity test state machine which requires link integrity pulses to be detected at certain intervals...

Page 259: ...COL Transmit MII Interface NBTCR NBDTR NBTSR NBTESR Tx FIFO 2048 bytes NBDR Receive MII Interface NBRCR NBDRR Multicast Filter Rx FIFO 2048 bytes NBMFxR MDC MDO MDOEN MDI Peripheral Clock MII Manageme...

Page 260: ...Port B Phys Addr 39 32 Register NBPA4R 0x0214 W xxxxxxxx Network Port B Phys Addr 47 40 Register NBPA5R 0x0215 W xxxxxxxx Network Port B Multicast Filter 7 0 Register NBMF0R 0x0218 R W xxxxxxxx Netwo...

Page 261: ...k Port B MII PHY Address Register NBMPAR 0x0255 R W 00000000 Network Port B MII Write LSB Register NBMWLR 0x0256 W 00000000 Network Port B MII Write MSB Register NBMWMR 0x0257 W 00000000 Network Port...

Page 262: ...MDC is generated by the Rabbit 5000 by dividing down the peripheral clock as selected in NBMCFR 22 2 3 Other Registers Table 22 1 Network Port MII Interface Section Signal Direction Function Transmit...

Page 263: ...gh level support for TCP IP and other protocols is beyond the scope of this manual but this section will describe the low level setup and operation of the 10 100Base T Ethernet peripheral The contents...

Page 264: ...ad the packet data from memory and write it to NBDR Write the buffer descriptor s address to the DMA s initial address registers see Chapter 21 for more information 2 Enable the DMA transfer by auto l...

Page 265: ...ead the interrupt status push af save status byte for later bit 4 a did transmit error occur jp nz handle_tx_err bit 4 a did transmit pause occur jp nz handle_pause_err done pop af ipres ret handle_tx...

Page 266: ...r program control A one in the corresponding table entry constitutes a multicast address match as far as the network port is concerned A table of one set of unique multi cast addresses corresponding t...

Page 267: ...of a frame to enable the subsequent transmission of the CRC The DMA automatically writes the last byte of the frame to this address Network Port B Transmit Status Register NBTSR Address 0x0202 Bit s V...

Page 268: ...cleared by a read of this register The individual interrupt enables are not affected 5 0 No transmit okay interrupt Read only 1 Transmit okay interrupt 4 0 No transmit error interrupt Read only 1 Tra...

Page 269: ...x backpressure 4 0 No operation 1 Transmit FIFO purge command 3 1 These bits are ignored and should always be written as zeros 0 0 No operation 1 Receive FIFO purge command Network Port B Transmit Pau...

Page 270: ...ion is complete 10 DMA request when FIFO is half full or frame reception is complete 11 DMA request when FIFO is one fourth full or frame reception is complete 5 0 Normal receiver operation 1 Place re...

Page 271: ...x Register NBPA0R Address 0x0210 NBPA1R Address 0x0211 NBPA2R Address 0x0212 NBPA3R Address 0x0213 NBPA4R Address 0x0214 NBPA5R Address 0x0215 Bit s Value Description 7 0 Write Byte of physical addre...

Page 272: ...disabled 3 Write Controls the state of the TX_ER pin if both network ports are disabled 2 Write Controls the state of the TX_EN pin if both network ports are disabled 1 Read Returns the state of the...

Page 273: ...ontrol frames 1 0 Pass normal receive frames only 1 Pass all receive frames normal or control 0 0 Disable receiver 1 Enable receiver Network Port B Configuration 1 Register NBCF1R Address 0x0241 Bit s...

Page 274: ...ames transmit and receive 1 0 Disable frame length checking 1 Enable frame length checking transmit and receive 0 0 Enable half duplex 1 Enable full duplex Network Port B Configuration 3 Register NBCF...

Page 275: ...C as specified by 802 3 Network Port B Gap 1 Register NBG1R Address 0x0247 Bit s Value Description 7 This bit is ignored and will always return zero when read 6 0 Non back to back interpacket gap Reco...

Page 276: ...eturn zeros when read 4 2 000 MII Management Clock is system clock divided by 4 001 This value is reserved and should not be used 010 MII Management Clock is system clock divided by 6 011 MII Manageme...

Page 277: ...ed and will always return zeros when read 4 0 MII register address Network Port B MII PHY Address Register NBMPAR Address 0x0255 Bit s Value Description 7 5 These bits are ignored and will always retu...

Page 278: ...ead 3 0 MII link okay 1 MII link fail 2 0 MII read data valid 1 MII read data not valid 1 0 MII not busy scanning 1 MII scan operation in progress 0 0 MII not busy performing a read or write cycle 1 M...

Page 279: ...forced whenever either SCFG pin is high 11 This bit combination is reserved and must not be used 5 2 0 These bits are reserved and should be written with zeros 1 0 00 Network Port C interrupts are dis...

Page 280: ...280 Rabbit 5000 Microprocessor User s Manual...

Page 281: ...is available providing support for separate receive and transmit antennas or switched antenna diversity reception The MAC processing is handed by a combination of the baseband processor and software...

Page 282: ...croprocessor User s Manual 23 1 1 Block Diagram 802 11b g Wireless LAN Transceiver Control Tx FIFO 2048 bytes Rx FIFO 2048 bytes Baseband Control Baseband Receiver 10 bit ADC AES Engine Baseband Trans...

Page 283: ...0000 Network Port C RSSI 3 Register NCRSSI3R 0x0A0F R 00000000 Network Port C Interrupt Mask Register NCIMR 0x0A10 R W 00000000 Network Port C Interrupt Status Register NCISR 0x0A14 R W 00000000 Netwo...

Page 284: ...Port C DTIM Period Register NCDTIMPR 0x0A58 R W xxxxxxxx Network Port C CFP Period Register NCCFPPR 0x0A59 R W xxxxxxxx Network Port C Listen Interval 0 Register NCLI0R 0x0A5A R W xxxxxxxx Network Po...

Page 285: ...Output VOUTPI Output I channel differential output VOUTNI Output Clock CLK_IN Input 20 MHz clock input Digital Auto Gain Correction VGA 4 0 Output Variable gain amplifier setting LNA 1 0 Output Linear...

Page 286: ...generate an interrupt can be selected in NCISR The wireless network port interrupt vector is shared with the Ethernet network port It is located in the IIR at offset 0x1E0 It can be set as Priority 1...

Page 287: ...tches the value written into the counter registers this allows an interrupt to be generated when a particular count is reached A 16 bit counter is used to record the time at which the event takes plac...

Page 288: ...asured by outputting a pulse at a pre cise time using Timer B to set the output time and capturing the output pulse with an input capture channel Once the phase relationship is known between the count...

Page 289: ...r 1 Register ICT1R 0x0058 R W 00000000 Input Capture Source 1 Register ICS1R 0x0059 R W xxxxxxxx Input Capture LSB 1 Register ICL1R 0x005A R xxxxxxxx Input Capture MSB 1 Register ICM1R 0x005B R xxxxxx...

Page 290: ...ters 24 2 4 Interrupts Each input capture channel can generate an interrupt whenever a start stop condition occurs The interrupt request is cleared when ICCSR is read The input capture interrupt vecto...

Page 291: ...nerate an interrupt 3 Configure the Input Capture Control Register ICCR to select the interrupt priority note that interrupts will be enabled once this value is set this step should be done last The f...

Page 292: ...andler read out the counter as an event timestamp Measure Time Interval from a Software Start to an External Event The following steps explain how to measure the time interval between a software start...

Page 293: ...ead 1 The Input Capture 2 counter has rolled over to all zeros 2 0 The Input Capture 1 counter has not rolled over to all zeros Read 1 The Input Capture 1 counter has rolled over to all zeros 7 2 Read...

Page 294: ...operation for Input Capture 2 6 0 Input Capture operation for Input Capture 1 1 Input Count operation for Input Capture 1 5 2 These bits are reserved and should be written with zero 1 0 00 Input Captu...

Page 295: ...urn the programmed match value 01 Latch the count on the Stop condition only 10 Latch the count on the Start condition only 11 Latch the count on either the Start or Stop condition 3 2 00 Ignore the s...

Page 296: ...p condition input 10 Parallel Port E used for Stop condition input 11 This bit combination is reserved and should not be used 1 0 00 Use port bit 1 for Stop condition input 01 Use port bit 3 for Stop...

Page 297: ...0x005F Bit s Value Description 7 0 Read The most significant eight bits of the latched Input capture count are returned In Counter operation if no latching condition is specified the value written to...

Page 298: ...298 Rabbit 5000 Microprocessor User s Manual...

Page 299: ...nputs to pre vent false counts The external signals are synchronized with an internal clock provided by the output of Timer A10 Each Quadrature Decoder channel accepts inputs from either the upper nib...

Page 300: ...t clock cycles Input capture may be used to measure the pulse width on the I inputs because they come from the odd numbered port bits The operation of the digital filter is shown below The Quadrature...

Page 301: ...0x0091 R W 00000000 Quad Decode Count 1 Register QDC1R 0x0094 R xxxxxxxx Quad Decode Count 1 High Register QDC1HR 0x0095 R xxxxxxxx Quad Decode Count 2 Register QDC2R 0x0096 R xxxxxxxx Quad Decode Co...

Page 302: ...0R The clock rate must be high enough that transitions on the inputs are sampled in different clock cycles In addition both the I and Q inputs go through a digital filter that rejects pulses shorter t...

Page 303: ...ote that interrupts will be enabled once this value is set The following actions occur within the interrupt service routine Since a Quadrature Decoder interrupt occurs when the counter rolls over dete...

Page 304: ...ead of this register 5 This bit always reads as zero 4 0 No effect on the Quadrature Decoder 2 Write only 1 Reset Quadrature Decoder 2 to all zeros without causing an interrupt 3 0 Quadrature Decoder...

Page 305: ...se Quadrature Decoder 1 to increment or decrement 01 Quadrature Decoder 1 inputs from Parallel Port D bits 1 and 0 10 Quadrature Decoder 1 inputs from Parallel Port E bits 1 and 0 11 Quadrature Decode...

Page 306: ...306 Rabbit 5000 Microprocessor User s Manual...

Page 307: ...n optionally be spread throughout the cycle to reduce ripple on the externally filtered PWM output The PWM outputs can be passed through a filter and used as a 10 bit D A converter The outputs can als...

Page 308: ...Rabbit 5000 are designed to work with fixed I O addresses To allow DMA control of the PWM a separate PWM Block Access Register PWBAR and PWM Block Pointer Register PWBPR are available The pointer regi...

Page 309: ...0R 0x0088 R W xxxxx00x PWM MSB 0 Register PWM0R 0x0089 R W xxxxxxxx PWM LSB 1 Register PWL1R 0x008A R W xxxxx00x PWM MSB 1 Register PWM1R 0x008B R W xxxxxxxx PWM LSB 2 Register PWL2R 0x008C R W xxxxx0...

Page 310: ...Interrupts The PWM can generate an interrupt for every PWM counter rollover every second roll over every fourth rollover or every eighth rollover This option is selected in PWL1R The interrupt request...

Page 311: ...andling Interrupts The following steps explain how an interrupt is set up and used 1 Write the vector to the interrupt service routine to the internal interrupt table 2 Configure PWL0R to select the P...

Page 312: ...Width Modulator interrupts use Interrupt Priority 3 0 0 PWM output High for single block 1 Spread PWM output throughout the cycle PWM LSB 1 Register PWL1R Address 0x008A Bit s Value Description 7 6 Le...

Page 313: ...output throughout the cycle PWM MSB x Register PWM0R Address 0x0089 PWM1R Address 0x008B PWM2R Address 0x008D PWM3R Address 0x008F Bit s Value Description 7 0 Most significant eight bits for the Pulse...

Page 314: ...314 Rabbit 5000 Microprocessor User s Manual...

Page 315: ...ternal I O transaction until the external device is ready to complete the transaction A timeout period can be defined to ensure that the processor is not held indef initely by a misbehaving external d...

Page 316: ...t on the memory bus alone or both buses It is also possible to shorten the read strobe by one clock cycle and the write strobe by one half a clock cycle by pulling in the trailing edge which guarantee...

Page 317: ...d cannot accept a transaction The Rabbit 5000 will then hold midway through the transaction until either the handshake signal goes inactive or a timeout occurs The timeout can be defined anywhere from...

Page 318: ...r IB2CR 0x0082 W 00000000 I O Bank 3 Control Register IB3CR 0x0083 W 00000000 I O Bank 4 Control Register IB4CR 0x0084 W 00000000 I O Bank 5 Control Register IB5CR 0x0085 W 00000000 I O Bank 6 Control...

Page 319: ...lel Ports C D or E each bank can be directed to the appropriate pin bank zero on PC0 PD0 or PE0 bank one on PC1 PD1 or PE1 etc The strobes will affect outputs on IOWR IORD and BUFEN at all times The I...

Page 320: ...s must be taken before using an I O strobe 1 Set the strobe type and timing for a particular device by writing to the appropriate IBxCR register for the I O bank desired 2 If signals other than IORD I...

Page 321: ...tive high I O transaction held until signal goes low 3 This bit is reserved and should be written with zero 2 0 000 Use Parallel Port E bit 0 for I O handshake 001 Use Parallel Port E bit 1 for I O ha...

Page 322: ...e I O handshake for I O Bank 2 1 0 Disable I O handshake for I O Bank 1 1 Enable I O handshake for I O Bank 1 0 0 Disable I O handshake for I O Bank 0 1 Enable I O handshake for I O Bank 0 I O Handsha...

Page 323: ...ignal is an I O chip select 01 The I signal is an I O read strobe 10 The I signal is an I O write strobe 11 The I signal is an I O data read or write strobe 3 0 Writes are not allowed to this bank Tra...

Page 324: ...able the slave port with SCS from Parallel Port E bit 7 011 Enable the external I O bus Parallel Port A is used for the data bus and Parallel Port B 7 2 is used for the address bus 100 This bit combin...

Page 325: ...tput 0 TXC 01 Parallel Port C bit 2 alternate output 1 I2 10 Parallel Port C bit 2 alternate output 2 TIMER C2 11 Parallel Port C bit 2 alternate output 3 TXF 3 2 00 Parallel Port C bit 1 alternate ou...

Page 326: ...2 PWM2 11 Parallel Port C bit 6 alternate output 3 TXE 3 2 00 Parallel Port C bit 5 alternate output 0 TXB 01 Parallel Port C bit 5 alternate output 1 I5 10 Parallel Port C bit 5 alternate output 2 P...

Page 327: ...ut 0 SCLKC 01 Parallel Port D bit 2 alternate output 1 I2 10 Parallel Port D bit 2 alternate output 2 TIMER C2 11 Parallel Port D bit 2 alternate output 3 TXF 3 2 00 Parallel Port D bit 1 alternate ou...

Page 328: ...2 PWM2 11 Parallel Port D bit 6 alternate output 3 TXE 3 2 00 Parallel Port D bit 5 alternate output 0 IA6 01 Parallel Port D bit 5 alternate output 1 I5 10 Parallel Port D bit 5 alternate output 2 P...

Page 329: ...tput 0 I2 01 Parallel Port E bit 2 alternate output 1 A22 10 Parallel Port E bit 2 alternate output 2 TIMER C2 11 Parallel Port E bit 2 alternate output 3 TXF 3 2 00 Parallel Port E bit 1 alternate ou...

Page 330: ...PWM2 11 Parallel Port E bit 6 alternate output 3 TXE 3 2 00 Parallel Port E bit 5 alternate output 0 I5 01 Parallel Port E bit 5 alternate output 1 LINK 10 Parallel Port E bit 5 alternate output 2 PW...

Page 331: ...the match occurred However because of the time required to perform a 24 bit address match in the processor a code execution breakpoint that is set on a single byte 2 clock instruction will not yet be...

Page 332: ...essor User s Manual 28 1 1 Block Diagram Address Compare Interrupt Request Breakpoint x BxCR BxM0R BxM1R BxM2R BxA0R BxA1R BxA2R Code Execution Data Read Data Write Address Interrupt Generation Addres...

Page 333: ...0000 Breakpoint 1 Address 0 2 Register B1AxR 0x031C x R W 00000000 Breakpoint 2 Address 0 2 Register B2AxR 0x032C x R W 00000000 Breakpoint 3 Address 0 2 Register B3AxR 0x033C x R W 00000000 Breakpoin...

Page 334: ...irst 28 3 Operation The following steps must be taken to enable breakpoints 1 Write the vector to the interrupt service routine to the external interrupt table 2 Write the desired breakpoint addresses...

Page 335: ...low breakpoint_isr push af ioi ld a BDCR determine which interrupts are pending and clear the interrupt request handle all breakpoints here reenable any breakpoints by writing to BDCR pop af ipres you...

Page 336: ...ddress 0x033B B4CR Address 0x034B B5CR Address 0x036B B6CR Address 0x037B Bit s Value Description 7 6 00 No Breakpoint x on execute address match 01 Breakpoint x on User Mode execute address match 10...

Page 337: ...kpoint x Address 1 Register B0A1R Address 0x030D B1A1R Address 0x031D B2A1R Address 0x032D B3A1R Address 0x033D B4A1R Address 0x034D B5A1R Address 0x036D B6A1R Address 0x037D Bit s Value Description 7...

Page 338: ...B0M1R Address 0x0309 B1M1R Address 0x0319 B2M1R Address 0x0329 B3M1R Address 0x0339 B4M1R Address 0x0349 B5M1R Address 0x0369 B6M1R Address 0x0379 Bit s Value Description 7 0 Breakpoint x Mask 15 8 A...

Page 339: ...e to reduce current draw by the attached memory devices Figure 29 1 shows a typical current draw as a function of the main clock frequency The values shown do not include any current consumed by exter...

Page 340: ...anual 29 1 1 Registers Register Name Mnemonic I O Address R W Reset Global Control Status Register GCSR 0x0000 R W 11000000 Global Power Save Control Register GPSCR 0x000D R W 00000000 Global Clock Do...

Page 341: ...y 8 with the peripheral clock at full speed If the clock doubler is enabled the options also include twice the main oscillator frequency and the main oscillator divided by 3 In addition the 32 kHz clo...

Page 342: ...width of the chip select the power consumption of the memory chip can be reduced without having any affect on the processor itself For reduced processor speeds based on the main oscillator a short chi...

Page 343: ...Chapter 29 Low Power Operation 343 CLK1 CLK A 23 0 D 7 0 CSx OEx valid T1 T2 Divide by 6 Mode CLK1 CLK A 23 0 D 7 0 CSx OEx valid T1 T2 Divide by 4 Mode...

Page 344: ...e chip select signal that is the width of a single 32 kHz clock 30 5 microseconds otherwise the timing is identical to the short chip select options based off the main oscillator Read strobe figures a...

Page 345: ...Chapter 29 Low Power Operation 345 32 kHz CLK A 23 0 D 7 0 CSx OEx valid T1 T2 Operation at 4 kHz 32 kHz CLK A 23 0 D 7 0 CSx OEx valid T1 T2 Operation at 8 kHz...

Page 346: ...346 Rabbit 5000 Microprocessor User s Manual 32 kHz CLK A 23 0 D 7 0 CSx OEx valid T1 T2 Operation at 16 kHz 32 kHz CLK A 23 0 D 7 0 CSx OEx valid T1 T2 Operation at 32 kHz...

Page 347: ...more when running off the 32 kHz oscillator When self timed chip selects are enabled the chip select is only active for a short selectable period of time ranging from 110 to 290 ns this can be enable...

Page 348: ...lock from the fats clock 010 Processor clock from the fast clock Peripheral clock from the fast clock 011 Processor clock from the fast clock divided by 2 Peripheral clock from the fast clock divided...

Page 349: ...11 110 ns self timed chip selects for read only 4 0 Normal chip select timing for read cycles 1 Short chip select timing for read cycles not available in full speed 3 0 Normal chip select timing for w...

Page 350: ...time 00100 9 ns nominal low time 00101 10 ns nominal low time 00110 11 ns nominal low time 00111 12 ns nominal low time 01000 13 ns nominal low time 01001 14 ns nominal low time 01010 15 ns nominal lo...

Page 351: ...the processor s I O registers and preventing memory writes to critical regions the user s code can run without the danger of locking up the processor to the point where it cannot be restarted remotel...

Page 352: ...0 I O Bank User Enable Register IBUER 0x0380 W 00000000 PWM User Enable Register PWUER 0x0388 W 00000000 Quad Decode User Enable Register QDUER 0x0390 W 00000000 External Interrupt User Enable Registe...

Page 353: ...lator 1 Register GCM1R 0x000B Secondary Watchdog Timer Register SWDTR 0x000C Global Power Save Control Register GPSCR 0x000D Global Output Control Register GOCR 0x000E Global Clock Double Register GCD...

Page 354: ...nabled and the pro cessor is in the User Mode If the processor is placed into Priority 3 either by an instruc tion or an interrupt it will respond as if it was set to Priority 2 When the System User M...

Page 355: ...pts to be used are set up for the User Mode critical memory regions are protected stack limits are set and the various system memory stack violation interrupts are enabled The processor then enters th...

Page 356: ...pheral and or interrupt from the System Mode If allowed the System Mode can create an interrupt vector as described in Section 30 3 7 that will execute the user code interrupt handler When the applica...

Page 357: ...ss 2 Write a 1 to bit 0 of EDMR to enable System User Mode 3 Execute the SETUSR instruction to enter User Mode After the User Mode is entered the limitations described earlier are in effect writes to...

Page 358: ...ser Mode or an interrupt occurs or SYSCALL or RST is executed to enter System Mode the current mode is pushed onto the SU register When a SURES is executed the previous mode is popped off the SU regis...

Page 359: ...t vectors to the same address as SYSCALL The difference is that it also pushes the value of the SU register as well as the return address onto the stack SRET is the companion instruction to SCALL it e...

Page 360: ...Mode before calling the User Mode interrupt handler An example of both system and user interrupt handling is shown in Figure 30 4 When enabled for User Mode access a peripheral interrupt if it is capa...

Page 361: ...e_isr jumped to from interrupt vector table handle interrupt sures reenter previous mode ipres restore previous interrupt priority ret usermode_isr jumped to from interrupt vector table still in syste...

Page 362: ...Enable Register PAUER Address 0x0330 Bit s Value Description 7 0 Disable User Mode access to Parallel Port A I O addresses 0x0030 0x0037 1 Enable User Mode access to Parallel Port A I O addresses 0x00...

Page 363: ...ode access to Parallel Port D I O addresses 0x0060 0x006F 6 0 These bits are reserved and should be written with zeros Parallel Port E User Enable Register PEUER Address 0x0370 Bit s Value Description...

Page 364: ...0x0083 2 0 Disable User Mode access to I O Bank 2 and internal I O address 0x0082 1 Enable User Mode access to I O Bank 2 and internal I O addresses 0x0082 1 0 Disable User Mode access to I O Bank 1...

Page 365: ...erved and should be written with zeros Analog User Enable Register AUER Address 0x03A8 Bit s Value Description 7 3 These bits are reserved and should be written with zeros 2 0 Disable User Mode access...

Page 366: ...B User Enable Register SBUER Address 0x03D0 Bit s Value Description 7 0 Disable User Mode access to Serial Port B I O addresses 0x00D0 0x00D7 1 Enable User Mode access to Serial Port B I O addresses...

Page 367: ...able User Mode access to Serial Port F I O addresses 0x00D8 0x00DF 1 Enable User Mode access to Serial Port F I O addresses 0x00D8 0x00DF 6 0 These bits are reserved and should be written with zeros E...

Page 368: ...368 Rabbit 5000 Microprocessor User s Manual...

Page 369: ...mA Core Current 50 MHz Wi Fi disabled 25 C 17 mA Core Current 32 768 kHz Wi Fi disabled 25 C 2 mA I O Ring I O Ring Supply Voltage 3 3 V VDDIO 3 0 V 3 3 V 3 6 V I O Ring Current 88 4736 MHz 25 C IIO 2...

Page 370: ...er Symbol Min Typ Max VBAT VBAT Supply Voltage VBAT 1 65 V 1 8 V 1 90 V VBAT Current rest of device powered rest of device powered down IVBAT 22 A 290 nA VBATIO VBATIO Supply Voltage rest of device po...

Page 371: ...ctrical Characteristics VDDCORE 1 8 V 10 VDDIO 3 3 V 10 TA 40 C to 85 C Parameter Symbol Min Typ Max Main Clock Frequency on CLKI fmain 100 MHz Real Time Clock Frequency on CLK32K fRTC 32 768 kHz Ethe...

Page 372: ...8 ns Clock to Memory Chip Select Delay TCSx 3 ns 6 ns Clock to Memory Read Strobe Delay TOEx 3 ns 6 ns Data Setup Time Tsetup 1 ns Data Hold Time Thold 0 ns Table 31 5 Preliminary Memory Write Time D...

Page 373: ...Read and Write Cycles Tadr Tadr Memory Read no wait states CLK A 19 0 Memory Write no extra wait states CLK A 19 0 valid T1 T2 T1 Tw T2 valid TOEx TOEx D 7 0 valid Thold Tsetup CSx OEx TCSx TCSx vali...

Page 374: ...e Cycles Early Output Enable and Write Enable Timing Tadr Tadr Memory Read no wait states CLK A 19 0 Memory Write no extra wait states CLK A 19 0 valid T1 T2 T1 Tw T2 valid TOEx TOEx D 7 0 valid Thold...

Page 375: ...ns 7 ns Clock to I O Buffer Enable Delay TBUFEN 3 ns 6 ns Data Setup Time Tsetup 1 ns Data Hold Time Thold 1 ns Table 31 7 Preliminary External I O Write Time Delays VDDCORE 1 8 V 10 VDDIO 3 3 V 10 T...

Page 376: ...IOCSx can be programmed to be active low default or active high Tadr External I O Read no extra wait states CLK A 23 0 IORD normal T1 Tw valid T2 BUFEN IORD early D 7 0 normal Tsetup Thold CSx IOCSx...

Page 377: ...States NOTE IOCSx can be programmed to be active low default or active high Tadr External I O Write no extra wait states CLK A 23 0 valid T1 Tw T2 IOCSx IOWR normal BUFEN valid D 7 0 CSx TCSx TIOCSx...

Page 378: ...number of wait states is used then the memory access time will be affected slightly When the clock spectrum spreader is enabled clock periods are shortened by a small amount depending on whether the...

Page 379: ...er is not enabled then every clock is shortened during the low part of the clock period The maximum shortening for a pair of clocks combined is shown in the table The gross memory access time is 2T wh...

Page 380: ...ed 80 of the nominal value should be used for the memory access time calculation clock 29 49 MHz so T 34 ns the clock doubler has a nominal delay of 16 ns see Table 31 8 resulting in a minimum clock l...

Page 381: ...least one wait state in the 16 bit mode Table 31 10 Some Recommended Clock Memory Configurations Input Frequency MHz Internal Frequency MHz Recommended Memory Timing Optimal Use 8 bit Devices 16 bit D...

Page 382: ...imum clock frequencies of about 100 MHz commercial or industrial If the clock doubler or spectrum spreader is used these maximum ratings must be reduced as shown in Table 31 11 11 0592 22 1184 12 ns 0...

Page 383: ...that it not be less than 2 ns Thus 3 ns must be added to the minimum period of 21 ns giving a minimum period of 24 ns and a maximum frequency of 41 6 MHz commercial Table 31 11 Preliminary Maximum Clo...

Page 384: ...duty cycle to obtain the highest clock speeds using the clock doubler you must use an external oscillator buffer that will allow for duty cycle adjustment by changing the resistance of the power and g...

Page 385: ...odes see Table 29 1 for more details Figure 31 6 shows a typical current draw as a function of the main clock frequency while Wi Fi is disabled The values shown do not include any current consumed by...

Page 386: ...lf timed chip selects At the low frequencies possible in the ultra sleepy modes as low as 2 kHz the external memory devices become signifi cant factors in the current consumption unless one of the sho...

Page 387: ...unning at 3 3 V normally A circuit to switch between a 1 8 2 0 V battery and the main power can use the RESOUT pin to switch the power source for the VBATIO pin R is a current limiting resistor that s...

Page 388: ...388 Rabbit 5000 Microprocessor User s Manual...

Page 389: ...IO VSSIO VSSIO VSSIO VSSIO VDDIO VSSIO VDD MDO MDOEN VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO A12 VSS VDDIO PE5 PE6 A33GND VIN8 VDDIO VDDIO 13 14...

Page 390: ...O VSSIO VDD SDATA SENB VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO A12 VSS VDDIO PE5 PE6 A33GND VIN8 VDDIO VDDIO 13 14 15 16 17 PC7 TESTIN0 VDD33 VS...

Page 391: ...32 3 BGA Package Outline 0 80 15 00 0 05 0 80 1 10 1 10 15 00 0 05 A B C D E F G H J K L M N P R T U 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BOTTOM VIEW Ball Pitch Ball Diameter 0 80 mm 0 40 mm A B...

Page 392: ...all Pitch mm Nominal Land Diameter mm Land Variation mm 0 40 0 45 0 35 0 80 0 35 0 35 0 30 Table 32 2 Design Considerations all dimensions in mm Key Feature Recommendation A Solder Land Diameter 0 356...

Page 393: ...Timer Timeout D7 STATUS Output Instruction Fetch First Byte E16 SMODE1 SMODE0 Input Bootstrap Mode Tamper Detect B9 A10 Chip Selects CS0 Output Memory Chip Select 0 H17 CS1 Output Memory Chip Select 1...

Page 394: ...RXD2 RXD3 TX_CLK Input C8 C12 D12 B12 C11 D10 A11 C9 D9 A8 MDIO Bidirectional J1 Wi Fi ACT_LED ANT_SEL ANT_SELB LNA0 LNA1 PA2G_ON PA5G_ON RX_ON RXHP SCLK SDATA SENB TX_ON VGA0 VGA1 VGA2 VGA3 VGA4 Out...

Page 395: ...A D Converter R6 T5 T3 U4 PD4 Clock C17 VOUTNI VOUTPI VOUTNQ VOUTPQ Output Analog Component 1 Fast D A Converter R14 P14 U15 U14 PD5 Clock C16 VIN8 Input Analog Component 2 Slow A D Converter A16 PD6...

Page 396: ...396 Rabbit 5000 Microprocessor User s Manual...

Page 397: ...TE FUNCTIONS A 1 Alternate Parallel Port Pin Outputs Table A 1 Alternate Parallel Port A and B Pin Outputs Pin Alternate Output Options Serial Clock External I O Bus Slave Port PA 7 0 ID 7 0 SD 7 0 PB...

Page 398: ...I7 PWM3 SCLKC PD6 TXA I6 PWM2 TXE PD5 IA6 I5 PWM1 RCLKE PD4 TXB I4 PWM0 TCLKE PD3 IA7 I3 TIMER C3 SCLKD PD2 SCLKC I2 TIMER C2 TXF PD1 IA6 I1 TIMER C1 RCLKF PD0 SCLKD I0 TIMER C0 TCLKF PE7 I7 PWM3 SCL...

Page 399: ...Quad rature Decoder Slave Port Serial Ports A D Serial Ports E F PA 7 0 SD 7 0 PB7 SLVATTN PB6 SCS PB5 SA1 PB4 SA0 PB3 SRD PB2 SWR PB1 SCLKA PB0 SCLKB PC7 RXA RXE PC6 PC5 RXB RCLKE PC4 TCLKE PC3 RXC...

Page 400: ...E3 DREQ1 QRD2A RXC RXF PE2 DREQ0 QRD2B SCLKC PE1 INT1 QRD1A RXD RCLKF PE0 INT0 QRD1B SCLKD TCLKF Table A 3 Alternate Parallel Port Pin Inputs continued Pin Input Capture I O Hand shake DMA External In...

Page 401: ...library a For 1 and 2 Mbps transmission rates the noise only exists for certain clock alignments with respect to other clocks in the design When Wi Fi is enabled the Wi Fi clock is checked for proper...

Page 402: ...e JR cc e Dynamic C does nothing to correct for this issue since an additional wait state will not significantly affect code 6 Read modify write instruction bug this bug has been found to exist in all...

Page 403: ...Appendix B Rabbit 5000 Errata 403 corrected Customers writing assembly code that accesses data in battery backed mem ory should avoid using these instructions to do so...

Page 404: ...404 Rabbit 5000 Microprocessor User s Manual...

Page 405: ...ort B 94 Parallel Port C 98 Parallel Port D 107 Parallel Port E 125 Parallel Port H 144 PWM 309 Quadrature Decoder 301 Rabbit 5000 16 reset 38 Serial Ports A D 173 Serial Ports E F 188 slave port 204...

Page 406: ...op events 287 interrupt priorities 84 interrupts 81 breakpoints 334 example ISR 335 DMA channels 231 234 236 example ISR 236 external interrupt vector table 83 external interrupts 85 86 block diagram...

Page 407: ...106 alternate output functions 105 block diagram 107 clocks 109 dependencies 109 interrupts 109 operation 110 overview 105 PDDR setup 105 register descriptions 111 registers 108 Parallel Port E 123 a...

Page 408: ...DMTCR 245 DTRCR 248 DTRDHR 248 DTRDLR 248 DyBCR 244 DyBU0R 249 DyBU1R 250 DyCR 252 DyDA0R 255 DyDA1R 255 DyDA2R 255 DyIA0R 250 DyIA1R 250 DyIA2R 250 DyL0R 253 DyLA0R 256 DyLA1R 256 DyLA2R 256 DyLnR 2...

Page 409: ...SxDLR 185 202 SxDR 180 197 SxER asynch mode 184 201 SxER clocked serial mode 185 SxER HDLC mode 202 SxLR 180 197 SxSR asynch mode 181 198 SxSR clocked serial mode 182 SxSR HDLC mode 199 TACR 155 TACS...

Page 410: ...nction Register 326 Parallel Port D Alternate High Register 328 Parallel Port D Alternate Low Register 327 Parallel Port D Function Register 328 Parallel Port E Alternate High Register 330 Parallel Po...

Page 411: ...rt A Data Regis ter 91 Slave Port Control Register 91 Parallel Port B 94 Parallel Port B Data Direc tion Register 95 Parallel Port B Data Regis ter 95 Slave Port Control Register 96 Parallel Port C 98...

Page 412: ...egister 197 Serial Port x Status Register asynch mode 198 Serial Port x Status Register HDLC mode 199 slave port 204 Slave Port Control Register 139 213 Slave Port Data x Registers 212 Slave Port Stat...

Page 413: ...l Port C 175 use of clocked Serial Port D 175 Serial Ports E F 187 asynchronous mode 187 block diagram 188 clocks 190 dependencies 190 HDLC data encoding 194 HDLC mode 187 DPLL counter 194 interrupts...

Page 414: ...ndencies 152 interrupts 150 153 example ISR 153 operation 153 overview 149 register descriptions 154 registers 152 reload register operation 149 Timer B 157 block diagram 157 clocks 158 dependencies 1...

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