Digi Rabbit 5000, User Manual

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68 Rabbit 5000 Microprocessor User’s Manual
ADD A, A ; a <= 00011100
SCF
SCF
ADC
A, H ; a <= 00011101
ADC A, H
LD L, A ; l <= 00011101
LD L, A
IOI ; two IOIs same as one
IOI
LD
(HL), B ; MACR <= 00000010
LD (HL), B ; dummy memory write (no /WE)
NOP ; required delay to start
NOP ; up the 16-bit bus
5.3.4 Separate Instruction and Data Space
To make better use of the 64 KB of logical space, an option is provided to map code and
data accesses in the same address space to separate devices. This is accomplished by
enabling the inversion of A16 and the most-significant bit of the bank select bits for accesses
in the root and data segments. Careful use of these features allows both code and data to
separately use up to 64 KB of logical memory.
The RAM segment register (RAMSR) provides a shortcut for updating code by accessing
it as data. It provides a “window” that uses the instruction address decoding when read or
written as data. This mapping will only occur when the RAMSR is within the root or data
segments; the RAMSR will be ignored if it is mapped to the stack segment or XPC
window.
The Rabbit 5000 Designer’s Handbook provides further details on the use of the separate
instruction and data space feature.
5.3.5 Memory Protection
Memory blocks may be protected at three separate granularities, as shown in Table 5-4.
Writes can be prevented to any memory bank by writing to MBxCR. Writes can be pre-
vented and trapped at a resolution of 64 KB by enabling protection for that block in the
appropriate WPxR register. For further control, two of those 64 KB blocks can be further
subdivided into 4 KB blocks by selecting them as the write protect segments A or B.
When a write is attempted to a block protected in WPxR, WPSxLR, or WPSxHR, a
Priority 3 write-protect interrupt occurs. This feature is automatically enabled by writing to
the block protection registers; to disable it, set all the write-protect block registers to zero.
Table 5-4. Memory Protection Options
Method Block Size Registers Used
Memory Bank 128 KB – 4 MB MBxCR, MECR
Write-Protect Blocks 64 KB WPCR, WPxR
Write Protect Segment A/B 4 KB WPSxR, WPSxLR, WPSxHR