Digi Rabbit 5000, User Manual

Page: 379 / 414

Chapter 31 Specifications 379
All important signals on the Rabbit 5000 are output-synchronized with the internal clock.
The internal clock is closely synchronized with the external clock, which is available on
the CLK pin. The delay in signal output depends on the capacitive load on the output lines.
In the case of the address lines, which are critically important for establishing memory
access time requirements, the capacitive loading is usually in the range of 25–100 pF, and
the load is due to the input capacitance of the memory devices and PC trace capacitance.
Delays are expressed from the waveform midpoint in keeping with the convention used by
memory manufacturers.
Table 31-9 lists the delays in gross memory access time for several values of VDD
IO
.
When the spectrum spreader is enabled with the clock doubler, every other clock cycle is
shortened or lengthened by a maximum amount given in the table above. The shortening
takes place by shortening the high part of the clock. If the doubler is not enabled, then
every clock is shortened during the low part of the clock period. The maximum shortening
for a pair of clocks combined is shown in the table.
The gross memory access time is 2T, where T is the clock period. To calculate the actual
memory access time, subtract the clock to address output time, the data in setup time, and
the clock period shortening due to the clock spectrum spreader from 2T.
Example Memory Access Time Calculation
•
clock = 29.49 MHz, so T = 34 ns
•
clock to address output delay = 6 ns (see Table 31-9)
•
data setup time = 1 ns
•
spectrum spreader is on in 1 ns mode, resulting in a loss of 3 ns worst-case (see
Table 31-9)
The access time is given by
access time = 2T - (clock to address) - (data setup) - (spreader delay)
= 68 ns - 6 ns - 1 ns - 3 ns
= 58 ns
Similarly, the gross output-enable access time is T + minimum clock low time (it is
assumed that the early output enable option is enabled). This is reduced by the spectrum
Table 31-9. Preliminary Data and Clock Delays
(V
DD
±10%, Temp. -40
°
C to 85
°
C)
VDD
IO
(V)
Clock to Address
Output Delay
(ns)
Data Setup
Time Delay
(ns)
Worst-Case
Spectrum Spreader Delay
(ns)
0.5 ns setting
no dbl / dbl
1 ns setting
no dbl / dbl
2 ns setting
no dbl / dbl
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