Digi Rabbit 5000, User Manual

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244 Rabbit 5000 Microprocessor User’s Manual
DMA y Buffer Complete Register (D0BCR) (Address = 0x0103)
(D1BCR) (Address = 0x0113)
(D2BCR) (Address = 0x0123)
(D3BCR) (Address = 0x0133)
(D4BCR) (Address = 0x0143)
(D5BCR) (Address = 0x0153)
(D6BCR) (Address = 0x0163)
(D7BCR) (Address = 0x0173)
Bit(s) Value Description
7:0 Read
The DMA increments a counter at the start of the next buffer. This count is
latched in this register and can be used, along with the
buffer unused count, to
determine the actual amount of data transferred by the DMA. This counter is
initialized by a start command or when the DMA is automatically rewound to the
initial address.
Write
Writing to this register loads the counter. This feature is intended only for testing,
because the DMA automatically resets the counter to all ones when fetching
from the initial address. The counter is incremented whenever the DMA fetches a
new buffer length value from a descriptor.
DMA Master Control Register (DMCR) (Address = 0x0104)
Bit(s) Value Description
7:4 These bits are reserved and should be written with zeros.
3:2 00
DMA transfers at Priority 0. No DMA transfers while CPU operates at Priority 3,
2, or 1.
01
DMA transfers at Priority 1. No DMA transfers while CPU operates at Priority 3
or 2.
10 DMA transfers at Priority 2. No DMA transfers while CPU operates at Priority 3.
11 DMA transfers at Priority 3. DMA transfers at any time.
1:0 00 DMA interrupts are disabled.
01 DMA interrupts use Interrupt Priority 1.
10 DMA interrupts use Interrupt Priority 2.
11 DMA interrupts use Interrupt Priority 3.