Digi Rabbit 5000, User Manual

Page: 171 / 414

Chapter 17 Serial Ports A – D 171
17. S
ERIAL
P
ORTS
A – D
17.1 Overview
Serial Ports A, B, C, and D are identical, except for the source of the data clock and the
transmit, receive, and clock pins. In addition to being used as a regular serial port, Serial
Port A can be used to bootstrap the processor. Each serial port can be used in the asynchro-
nous or the clocked serial mode with an internal or external clock.
In the asynchronous mode, either 7 or 8 data bits can be transferred, and a parity bit and/or
a ninth data bit can be appended as well. Parity and the ninth data bits are also detected
when they are received. The asynchronous mode is full-duplex, while the clocked mode
can be half or full-duplex.
Both transmit and receive have one byte of buffering — a byte may be read while another
byte is being received, or the next byte to be transmitted can be loaded while the current
byte is still being transferred out.
The status of each serial port is available in its Serial Port Status Register (SxSR), and
contains information on whether a received byte is available, the receive buffer was over-
run, a parity error was received, the transmit buffer is empty or busy sending a byte, and
the state of the ninth data bit (whether it is an address bit or a stop bit). Each serial port has
a separate interrupt vector that will be requested whenever the transmit buffer is emptied
or the receive buffer contains a full byte.
All four common SPI clock modes are supported, and the bit order of the data may be either
MSB or LSB first. The transmit and receive operations are under program control as well.
NOTE: The maximum external serial clock rate for the SPI port is 1/6 of the peripheral
clock rate.