Digi Rabbit 5000, User Manual

Page: 41 / 414

Chapter 3 Reset and Bootstrap 41
The processor checks the SMODE and SYSCFG0 pins after the /RESET signal is inactive.
Table 3-2 summarizes what happens.
If both SMODE pins are zero, the Rabbit 5000 begins fetching instructions from the
memory device mapped into memory bank 0. When SYSCFG0 is low, memory bank 0 is
set to /CS0 and /OE0. If SYSCFG0 is high, memory bank 0 is set to /CS3 and /OE0, and
the internal SRAM is selected in 16-bit mode. If a 16-bit memory is used in memory bank 0,
the first section of code must immediately select the 16-bit bus mode. Chapter 5 provides
a short sample program to do this.
If either of the SMODE pins is high, the processor will enter the bootstrap mode and
accept triplets from Serial Port A, the serial flash bootstrap port, or the slave port, depend-
ing on the SMODE pin selection. It is good practice to place pulldown resistors on the
SMODE pins to ensure the proper operation of your design.
In the bootstrap mode, the processor inhibits the normal memory fetch, and instead fetches
instructions from a small internal boot ROM. This program reads triplets of three bytes
from the selected peripheral. The first byte is the most-significant byte of a 16-bit address,
the second byte is the least-significant byte of the address, and the third byte is the data to
be written. If the uppermost bit of the address is 1, then the address is assumed to be an
internal register address instead of a memory address, and the data are written to the
appropriate register instead. For example, a triplet of (0x04, 0x34, 0x5A) will write 0x5A
to logical memory address 0x0434, while a triplet of (0x80, 0x34, 0x5A) will write 0x5A
to processor register 0x34. Processor registers with addresses above 0xFF are not accessi-
ble in the bootstrap mode.
The boot ROM program waits for data to be available; each byte received automatically
resets the watchdog timer with a 2-second timeout. Bytes must be received quickly
enough to prevent timeout (or the watchdog must be disabled).
The device checks the state of the SMODE pins each time it jumps back to the start of the
ROM program and responds according to the current state. In addition, by setting bit 7 of
Table 3-2. SMODE Pin Settings
SMODE Pins [1,0] SYSCFG0 Operation
00 0
No bootstrap; code is fetched from address 0x0000
on /CS0, /OE0.
00 1
No bootstrap; code is fetched from address 0x0000
on /CS3, /OE0. The internal SRAM is enabled as a
16-bit memory device.
01 x Bootstrap from the slave port.
10 x Bootstrap from Serial Port A, serial flash mode.
11 x Bootstrap from Serial Port A, asynchronous mode.