Digi Rabbit 5000, User Manual

Page: 235 / 414

Chapter 21 DMA Channels 235
21.3 Operation
It is possible to set up and start a DMA operation by writing directly to all the relevant
address, length, and control registers, but it is expected that the typical operation would be
to create a buffer descriptor in memory, write the address of that descriptor to the initial
address registers (DyIAnR), and use a write to DMALR to auto-load the values from memory
into the registers and start the transfer. The DMA transfer will then continue reading buffer
descriptors until a buffer-marked halt is completed.
The descriptor can be either 12 or 16 bytes in length; a bit in the channel control byte (which
corresponds to DyCR) selects whether the link address is present or not. The processor
skips the read of those bytes if a 12-byte descriptor is selected, and always skips the reads
of the bytes marked “not used.”
It is possible to abort a DMA transfer by writing the appropriate bit to the halt register,
DMHR. It is also possible to restart a DMA transfer using the already-loaded register
values by writing to DMCSR.
The following steps explain how to set up a DMA channel.
1. Select the DMA transfer and interrupt priorities by writing to DMCR.
2. Select the DMA channel priority, maximum bytes per burst, and minimum clocks
between bursts by writing to DMTCR.
3. Write the interrupt vector for the interrupt service routine to the external interrupt table.
4. Enable an external request line by writing to DMR0CR or DMR1CR. Make sure that
the pin selected is set up as an input. Note that this enable will be logical-ANDed to any
internal DMA enables if the DMA transfer is to/from an internal peripheral.
5. Enable the internal-timed transfer request by writing to DTRCR. Select the divider value
by writing to DTRDLR and DTRDHR. Note that this enable will be logical-ANDed to
any internal DMA enables if the DMA transfer is to/from an internal peripheral.
6. Select a byte to terminate the transfer on by writing to the appropriate DyTBR and
DyTMR registers.
Table 21-1. DMA Buffer Descriptor
Byte 0 Byte 1 Byte 2 Byte 3
Bytes 0–3
Special Channel
Control /
Frame Status
Channel Control Buffer Length [15:0]
Bytes 4–7 Source Address [23:0] Not Used
Bytes 8–11 Destination Address [23:0] Not Used
Bytes 12–15 Link Address [23:0] Not Used