Digi Rabbit 5000, User Manual

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150 Rabbit 5000 Microprocessor User’s Manual
generate interrupts but the timers themselves cannot. Furthermore, these timers cannot be
cascaded with Timer A1.
The individual Timer A capabilities are summarized in the table below. There is a bit in
the control/status register to disable all ten timers globally.
There is one interrupt vector for Timer A and a common interrupt priority. A common status
register (TACSR) has bits for Timers A1–A7 that indicate if the output pulse for that timer
has taken place since the last read of the status register. These bits are cleared when the status
register is read. No bit will be lost. Either it will be read by the status register read or it will
be set after the status register read is complete. If a bit is on and the corresponding interrupt
is enabled, an interrupt will occur when priorities allow. However, a separate interrupt is not
guaranteed for each bit with an enabled interrupt. If the bit is read in the status register, it is
cleared and no further interrupt corresponding to that bit will be requested. It is possible that
one bit will cause an interrupt, and then one or more additional bits will be set before the sta-
tus register is read. After these bits are cleared, they cannot cause an interrupt. The proper
rule to follow is for the interrupt routine to handle all bits that it sees set.
Timer
Cascade
from A1
Interrupt Associated Peripheral
A1 No Yes Parallel Ports D–E, Timers B–C
A2 Yes Yes Serial Port E
A3 Yes Yes Serial Port F
A4 Yes Yes Serial Port A
A5 Yes Yes Serial Port B
A6 Yes Yes Serial Port C
A7 Yes Yes Serial Port D
A8 No No Input Capture
A9 No No Pulse-Width Modulator
A10 No No Quadrature Decoder