Digi Rabbit 5000, User Manual

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378 Rabbit 5000 Microprocessor User’s Manual
31.3.5 Memory Access Times
In computing memory requirements, the important considerations are the address access
time, output-enable access time, and minimum write-pulse required. Increasing the clock
doubler delay increases the output-enable time, but decreases the memory write-pulse
width. The early write-pulse option can be used to ensure a long-enough write pulse, but
then it must be ensured that the write pulse does not begin before the address lines have
stabilized.
The clock doubler has an affect on the memory access times. It works by ORing the clock
with a delayed version of itself. The nominal delay varies from 3 to 20 ns, and is set under
program control. Any asymmetry in the main clock input before it is doubled will result in
alternate clocks having slightly different periods. Using the suggested oscillator circuit,
the asymmetry is no worse than 52%–48%. This results in a given clock being shortened
by the ratio 50/52, or 4% worst-case. The memory access time is not normally affected
because the memory bus cycle is two clocks long and includes both a long and a short
clock, resulting in no net change arising from asymmetry. However, if an odd number of
wait states is used, then the memory access time will be affected slightly.
When the clock spectrum spreader is enabled, clock periods are shortened by a small
amount, depending on whether the “normal” or the “strong” spreader setting is used, and
depending on the operating voltage. If the clock doubler is used, the spectrum spreader
affects every other cycle and reduces the clock high time. If the doubler is not used, then the
spreader affects every clock cycle, and the clock low time is reduced. Of course, the spec-
trum spreader also lengthens clock cycles, but only the worst-case shortening is relevant for
calculating worst-case access times. The numbers given for clock shortening with the dou-
bler disabled are the combined shortening for two consecutive clock cycles, worst case.
The required memory address and output-enable access time for some typical clock
speeds are given in Table 31-8 below. It is assumed that the clock doubler is used, that the
clock spreader is enabled in the normal mode, that the memory early output-enable is on,
and that the address bus has a load of 60 pF.
Table 31-8. Preliminary Memory Requirements
(VDD
CORE
= 1.8 V
±
10%, VDD
IO
= 3.3 V
±
10%, T
A
= -40
°
C to 85
°
C,
address bus loading = 60 pF)
Clock
Frequency
(MHz)
Period
(ns)
Clock Doubler
Nominal Delay
(ns)
Memory Address
Access
(ns)
Memory Output-
Enable Access
(ns)
22.11 45 20 78 51
29.49 34 16 56 36
44.24 22.5 10 33.5 22
58.98 17 6 22 19