Chapter 4 Parameters
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VFD-L-I Series
Revision July 2009, SW V1.1
4-55
STX ‘:’
‘0’
ADR 1
ADR 0
‘1’
‘0’
CMD1
CMD0
‘3’
‘0’
‘4’
‘0’
Starting data address
‘1’
‘0’
‘0’
‘0’
Number of data
‘1’
‘F’
LRC CHK 1
LRC CHK 0
‘6’
CR
END1
END0
LF
01H+03H+04H+01H+00H+01H=0AH, the 2’s-complement negation of 0AH is
F6
H.
RTU mode:
CRC (Cyclical Redundancy Check) is calculated by the following steps:
Step 1:
Load a 16-bit register (called CRC register) with FFFFH.
Step 2:
Exclusive OR the first 8-bit byte of the command message with the low order byte of
the 16-bit CRC register, putting the result in the CRC register.
Step 3:
Examine the LSB of CRC register.
Step 4:
If the LSB of CRC register is 0, shift the CRC register one bit to the right with MSB zero
filling, then repeat step 3. If the LSB of CRC register is 1, shift the CRC register one
bit to the right with MSB zero filling, Exclusive OR the CRC register with the
polynomial value A001H, then repeat step 3.
Step 5:
Repeat step 3 and 4 until eight shifts have been performed. When this is done, a
complete 8-bit byte will have been processed.
Step 6:
Repeat step 2 to 5 for the next 8-bit byte of the command message. Continue doing this
until all bytes have been processed. The final contents of the CRC register are the
CRC value. When transmitting the CRC value in the message, the upper and lower
bytes of the CRC value must be swapped, i.e. the lower order byte will be transmitted
first.
Summary of Contents for VFD-L-I Series
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