H O S T I N T E R F A C E
Data Device Corporation
DS-BU-67301B-G
1/14
80
Figure 40. Synchronous, Non-Multiplexed Address - 16-bit Sequential Burst Memory
Read Transfer Timing
Figure 40 Notes:
1. A one-clock-cycle wide pulse of nDATA_STRB (low) when nSELECT is
asserted (low) and valid address presented initiates the sequential burst read
transfer. nSELECT must be asserted low through the full burst cycle. The
nDATA_RDY output is initially asserted low on the same clock cycle when the
Total-AceXtreme®
drives the first valid 16-bit data word on the data bus.
CPU_nLAST must be asserted high until the last 16-bit word is to be read. On
the rising clock edge following CPU_nLAST asserting low, the last 16-bit word
is removed (tri-stated) from the data bus, and nDATA_RDY is de-asserted
(high). At this time (or later) nSELECT must be de-asserted high, completing
the burst read transfer.
2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full
transfer cycle.
3. Unless the
Total-AceXtreme
command FIFO is full, CPU_nSTOP is not
asserted, and will remain high.
MSW_nLSW
HOST_CLK
nDATA_RDY
CPU_DATA
CPU_WORD_EN[1:0]
RD_nWR
MEM_nREG
CPU_ADDR
nDATA_STRB
nSELECT
CPU_nLAST
CPU_nSTOP
tCLK
tDD
tRDD
Data
Data
Data
Data
Data
Data
Data
Data
tRDD
tCS
tDH
tCH
tAS
tAS
tAS
Address
tAS
tAH
tAH
tAH
tLH
tAH
tAS
tAH
tAH
tLS
tLS
tSS
tSH
tSHC
tWait
