DDC Total-AceXtreme BU-67301B, Design Manual

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H O S T I N T E R F A C E
Data Device Corporation DS-BU-67301B-G
www.ddc-web.com 1/14
41
Asynchronous Timing Information
Table 6 lists the eight Asynchronous mode timing diagrams, Figure 11 through Figure
18, while Table 7 lists the timing parameters that are applicable for these diagrams.
Table 6. Asynchronous Transfers
Non-Multiplexed or
Multiplexed
Address/Data
32-bit or 16-bit Read or Write Timing Diagram
Non-Multiplexed 32 Read Figure 11
Non-Multiplexed 32 Write Figure 12
Non-Multiplexed 16 Read Figure 13
Non-Multiplexed 16 Write Figure 14
Multiplexed 32 Read Figure 15
Multiplexed 32 Write Figure 16
Multiplexed 16 Read Figure 17
Multiplexed 16 Write Figure 18
Table 7. Asynchronous Timing Information
REF DESCRIPTION NOTES
Timing
Characteristics
UNITS
MIN TYP MAX
t
SS
nSELECT setup time prior to nDATA_STRB low (for non-
multiplexed address) or ADDR_LAT high (for multiplexed
address) 0 ns
t
SH
nSELECT hold time following nDATA_STRB high 0 ns
t
AS
CPU_ADDR, MEM_nREG, RD_nWR, and CPU_WORD_EN
valid setup time prior to nDATA_STRB low (for non-multiplexed
address) or ADDR_LAT high (for multiplexed address) 10 ns
t
AH
CPU_ADDR, MEM_nREG, RD_nWR, and CPU_WORD_EN
valid hold time following nDATA_STRB high (for non-multiplexed
address) or ADDR_LAT low (for multiplexed address) 7 ns
t
Wait
(32-bit read or
first 16-bit read)
Maximum delay from nDATA_STRB falling edge to nDATA_RDY
falling edge 70 ns
t
Wait
(second 16-bit
read)
Maximum delay from nDATA_STRB falling edge to nDATA_RDY
falling edge 40 ns
t
Wait
(write)
Maximum delay from nDATA_STRB falling edge to nDATA_RDY
falling edge 40 ns
t
DD
During READ operations: CPU_DATA valid delay following falling 10pF load 5 ns