H O S T I N T E R F A C E
Data Device Corporation
DS-BU-67301B-G
1/14
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For the first word transfer for 16-bit Synchronous single-word register write
accesses, nDATA_RDY will assert low when the
Total-AceXtreme
internally
latches
the data transferred over CPU_DATA(15:0) and de-asserts high on the
HOST_CLK rising edge after nSELECT is sampled high. For the second word
transfer, nDATA_RDY asserts low for a single host clock cycle when the
Total-
AceXtreme®
internally latches
the data transferred over CPU_DATA(15:0).
For Synchronous burst memory read transfers, nDATA_RDY is initially asserted
low on the same host clock cycle that the
Total-AceXtreme
drives the first data
word on to CPU_DATA(31:0) or CPU_DATA(15:0). For the case of Synchronous
burst memory write transfers, nDATA_RDY is initially asserted low on the same
host clock cycle that the
Total-AceXtreme
latches data driven by the host over
CPU_DATA(31:0), CPU_DATA(31:16), or CPU_DATA(15:0). In either case,
nDATA_RDY will continue to assert low through the end of the host clock cycle
for the last word read by the host for a read burst transfer, or latched by the
Total-AceXtreme
for a write burst transfer. That is, nDATA_RDY will assert low
until one host clock cycle after the host CPU has asserted CPU_nLAST low.
•
nINT:
This is the interrupt request output for the
Total-AceXtreme’s
parallel CPU
interface. The operation of nINT is software-programmable for active high or
active low, two-state or open drain, and level or pulse. For the case of a pulse
interrupt, the pulse width is also programmable. The nINT pulse width may be
programmed for a value between 3 and 65,537 clock cycles. The clock used for
formulating the nINT pulse width will be the
Total-AceXtreme’s
internal 160 MHz
clock for the Asynchronous CPU interface mode, and the HOST_CLK input for
the Synchronous CPU interface mode.
•
CPU_nSTOP:
In Synchronous mode, this active low signal is used to indicate the occurrence of
a “FIFO–full” condition, thereby terminating the current transfer. This condition
will only occur following the occurrence of a “full” condition for the
Total-
AceXtreme’s
command (input) FIFO. For more information on this operation,
refer to paragraph 6.4.2 and Figure 47.
CPU_nSTOP will also be asserted low along with nDATA_RDY at the completion
of a single-word Synchronous register (but not memory) read transfer. In either
case, CPU_nSTOP will remain low until nSELECT is de-asserted high. For all
other correctly completed Synchronous transfers, CPU_nSTOP will remain high.
In Asynchronous mode, CPU_nSTOP is not used and will remain high.
