Data Device Corporation
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DS-BU-67301B-G
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5
BUILT-IN TEST
5.1 Total-AceXtreme® Self-Test
The
Total-AceXtreme®
provides both on-line and off-line tests that can be used to
verify correct operation.
On-Line tests include a continuous loopback test which verifies that the waveform
that is received from the bus matches what was intended to be transmitted on the
bus, as well as verification that received commands and data are correctly formatted.
Off-line tests include a modification of the loopback test that disconnects the
transmitters and is received internally (before the transceiver) in order to test the BC
logic without disrupting the 1553 bus, along with an RT protocol test.
There is also a Bus A to Bus B loopback test, which requires that the two buses be
connected together externally to verify the entire transmission and reception path,
including the transceivers, transformers, and the rest of the signal path. The
Total-
AceXtreme
BC mode also includes a memory self-test.
In addition to the self-test features built into the
Total-AceXtreme
1553 core, the
Total-AceXtreme
offers low-level Built-in-Test (BIST) functions that cover the
internal memory blocks, 1553 core, and IRIG module. The shared RAM, scratchpad
RAM, and microcode ROM can be tested simultaneously or independently, but once
a test is started, it must either be allowed to complete or canceled before starting
another test. There is also a full internal scan test of the 1553 and IRIG modules
which provides 90% coverage against faults.
Beyond all of the included hardware test options, the internal registers and shared
RAM are fully accessible by the host processor and, therefore, may be tested by
software routines that implement checkerboard, walking zero, walking one and
counting patterns.
5.2 JTAG Boundary Scan
The
Total-AceXtreme
contains an IEEE 1149.1 compliant JTAG port that supports
Boundary Scan for board-level verification of assemblies. When used in a board
assembly with other compliant chips, this allows an automatic tester to determine that
all signal paths between those chips are bonded correctly with no shorts or opens by
running a series of test vectors.
All logic input signals can be sampled and all logic outputs can be selectively driven
high, low, or tri-stated as desired by shifting the data through the JTAG port. The
