H O S T I N T E R F A C E
Data Device Corporation
DS-BU-67301B-G
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MSW_nLSW
HOST_CLK
CPU_DATA
CPU_WORD_EN[1:0]
RD_nWR
MEM_nREG
CPU_ADDR
nDATA_STRB
nSELECT
CPU_nLAST
tCLK
tDD
tRDD
Data
Data
Data
Data
Data
Data
Data
Data
tRDD
tCS
tDH
tCH
tAS
tAS
tAS
Address
tAS
tAH
tAH
tAH
tLH
tAH
tAS
tAH
tAH
tLS
tLS
tSS
tSH
tSHC
tWait
Figure 45. Synchronous, Multiplexed Address - 16-bit Sequential Burst Memory Read
Transfer Timing
Figure 45 Notes:
1. With nSELECT asserted low and valid address presented on CPU_DATA, a
positive pulse on the ADDR_LAT input satisfying t
ALS
and T
AHL
will result in the
Total-AceXtreme®
latching the starting address for the sequential burst. One
clock cycle later, a one-clock-cycle wide pulse of nDATA_STRB (low) while
nSELECT remains asserted (low) initiates the sequential burst transfer.
nSELECT must be asserted low through the remainder of the burst cycle. The
nDATA_RDY output is initially asserted low on the clock cycle prior to the
cycle in which the
Total-AceXtreme
reads the first data word from the data
bus. CPU_nLAST must be asserted high until the last word is to be written. On
the rising clock edge following CPU_nLAST asserting low, the
Total-
AceXtreme
reads the last word from the data bus, and nDATA_RDY is de-
asserted (high). At this time (or later) nSELECT must be de-asserted high,
completing the burst write transfer.
2. For 16-bit accesses, CPU_WORD_EN[1:0] must be ‘11’ through the full
transfer cycle.
3. Unless the
Total-AceXtreme
command FIFO is full, CPU_nSTOP is not
asserted, and will remain high.
