DDC Total-AceXtreme BU-67301B, Design Manual

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T O T A L - A C E X T R E M E ® S I G N A L S
Data Device Corporation DS-BU-67301B-G
www.ddc-web.com 1/14
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Table 19. CPU Data Bus
Signal Name BAL
L
Pullup/
Pulldown
Description
CPU_ADDR(06) (I) J3 None
CPU_ADDR(05) (I) H3 None
CPU_ADDR(04) (I) L2 None
CPU_ADDR(03) (I) E1 None
CPU_ADDR(02) (I) J4 None
CPU_ADDR(01) (I) K5 None
CPU_ADDR(00) (I) M3 None
NC J2 None Not Used / No User Connection
NC A9 None Not Used / No User Connection
nMSTCLR (I) B6 None Master Clear. Negative true Reset input. Asserting this signal low resets all
internal logic. However, this signal does
not reset the PLL that generates the
internal 160 MHz clock.
nSELECT (I) T2 50k Pullup Device Select.
Chip select to select this device. This signal should be asserted active low
throughout the entire transfer cycle. It may be tied low if this device is the only
device in the system.
Generally connected to a CPU address signal or to a CPU address decoder
output to select the Total-AceXtreme for a transfer to/from either RAM or
register.
nDATA_STRB (I) M6 50k Pullup Strobe Data.
For non-multiplexed asynchronous mode, nDATA_STRB must be asserted
throughout each 32-bit or 16-bit data transfer, until nDATA_RDY is asserted.
For multiplexed asynchronous mode, nDATA_STRB must be asserted
following the address portion of the transfer cycle, that is following the falling
edge of the ADDR_LAT input signal, and maintained low throughout the data
portion 32-bit or 16-bit data transfer, that is until nDATA_RDY is asserted.
For synchronous non-multiplexed single or sequential burst transactions,
nDATA_STRB must be asserted low for exactly one clock cycle and
synchronous to the first active low chip select and valid address.
For random burst transactions, nDATA_STRB should be synchronous to the
first active low chip select and valid address, and remain low indicating a new
address is present for each clock cycle.
For synchronous multiplexed mode, nDATA_STRB should be asserted low for
exactly one host clock cycle to initiate first data cycle of the CPU transfer, on
the host clock cycle following the address transfer (ADDR_LAT).
RD_nWR (I) J6 50k Pullup Read/Write.
Indicating the type of transfer: ‘1’ to read or ‘0’ to write. This signal should be
active throughout the entire transfer cycle (See POL_SEL for active high/low
options).