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H O S T I N T E R F A C E

Data Device Corporation

DS-BU-67301B-G

www.ddc-web.com

1/14

91

Table 13. PCI Bus Interface Signals

Signal Name

DIR

Description

HOST_CLK

I

PCI Clock

Input clock from the host. Can be up to 66MHz

PCI_AD[31:0]

I/O

PCI Address / Data

GNT#

I

Bus Master Grant

Indicates to the Total-AceXtreme that access to the bus has been
granted by the PCI Arbiter. This is only required for DMA/PCI Initiator
transactions.

REQ#

O

Bus Master Request

Request to the bus Arbiter for control of the PCI bus. This is only
required for DMA/PCI Initiator transactions.

PERR#

I/O

Parity Error

This pin is used for reporting parity errors. It does not indicate Parity
errors during the Address phase.

IDSEL

I

Initialization Device Select

This signal is used as a chip select during configuration read or write
operations. It should be connected to an upper PCI A/D line or an
individual control signal from the PCI Bus Controller. The connection is
system specific.

DEVSEL#

I/O

Device Select

This signal is sourced by the active target upon decoding that its address
and bus commands are valid.

STOP#

I/O

PCI Stop.

This signal

indicates the current target is requesting the master to

stop the current transaction.

IRDY#

I/O

Initiator Ready

This signal

indicates that the initiating agent is able to complete the

current data phase of the transaction.

TRDY#

I/O

PCI Target Ready

This signal indicates the ability of the target agent’s (selected device)
ability to complete the current data phase of the transaction.

FRAME#

I/O

PCI Frame

This signal is driven by the current master to indicate the
beginning and duration of an access.

PAR

I/O

PCI Parity

This signal

represents even3 parity across AD[31::00] and C/BE[3::0]#.

C/BE[3:0]#

I/O

PCI Command and Byte Enables

These signals are multiplexed on the same PCI pins. During the address
phase of a transaction, C/BE[3::0]# define the bus command.
During the data phase, C/BE[3::0]# are used as Byte Enables.

SERR#

I/O

PCI System Error

This signal is used for reporting address parity errors, data parity
errors on the Special Cycle command, or any other system
error where the result will be catastrophic.

INTA#

O

Interrupt

This pin is a level sensitive, active low interrupt to the host.

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Summary of Contents for Total-AceXtreme BU-67301B

Page 1: ...PU Interface Access Time as low as 12 5ns DMA Engine with 264MB sec Burst Transfer Rate 1 Dual Redundant MIL STD 1553 Channel BC or Multi RT with Concurrent Bus Monitor Supports MIL STD 1553 A B and M...

Page 2: ...nversion and data interface needs DDC supplies MIL STD 1553 board level products in a variety of form factors including AMC USB PCI cPCI PCI 104 PCMCIA PMC PC 104 PC 104 Plus VME VXI and ISAbus cards...

Page 3: ...te at http www ddc web com for the latest information All rights reserved No part of this Data Sheet may be reproduced or transmitted in any form or by any mean electronic mechanical photocopying reco...

Page 4: ...Hottest Die Figure 5 Eliminated MT 100 s Timer 16 bit block Added Figure 56 Timing of CLK_IN Logic_VDDIO PLL_ 1 8V and Core_ 1 8V Figure 58 Made corrections Figure 59 Made corrections Table 22 Changed...

Page 5: ...gs 22 4 3 Local Timer 22 4 4 DMA Controller 23 5 BUILT IN TEST 25 5 1 Total AceXtreme Self Test 25 5 2 JTAG Boundary Scan 25 6 HOST INTERFACE 27 6 1 Host Interface Configuration Options 27 6 2 Paralle...

Page 6: ...B G www ddc web com 1 14 iv 11 TOTAL ACEXTREME SIGNALS 108 11 1 Signal Descriptions and Pinout by Functional Groups 108 11 2 Host Interface Signals 110 11 3 Pinout Table 124 11 4 Total AceXtreme Pin D...

Page 7: ...32 bit Multiplexed Address Synchronous Interface 57 Figure 21 16 bit Non Multiplexed Address Synchronous Interface 58 Figure 22 16 bit Multiplexed Address Synchronous Interface 59 Figure 23 Synchrono...

Page 8: ...ng 85 Figure 46 Synchronous Multiplexed Address 16 bit Sequential Burst Write Transfer Timing 86 Figure 47 Timing for Assertion of CPU_nSTOP Output During Synchronous Burst Write Transfer 87 Figure 48...

Page 9: ...Configuration Options 55 Table 9 Single Word Synchronous Transfers 60 Table 10 Synchronous Burst Transfers 60 Table 11 Synchronous Timing Parameters 61 Table 12 Total AceXtreme PCI Interface Character...

Page 10: ...s indicates user entered text or commands 1 2 Standard Definitions E 2 MA Extended Enhanced Mini ACE EMACE Enhanced Mini ACE BC MIL STD 1553 Bus Controller MT MIL STD 1553 Monitor Terminal RT MIL STD...

Page 11: ...DC by the following US Toll Free Technical Support 1 800 DDC 5757 ext 7771 Outside of the US Technical Support 1 631 567 5600 ext 7771 Fax 1 631 567 5758 to the attention of DATA BUS Applications DDC...

Page 12: ...Xtreme s shared memory and PCI host space The device provides a dual redundant MIL STD 1553 channel with very low power less than 1 W maximum dissipation It includes an IEEE 1149 1 compliant JTAG test...

Page 13: ...48 bit 100ns Time Stamp IRIG 106 Chapter 10 Monitor 1553 Bus Controller BC Highly Autonomous Controller with 32 Instruction Set Streaming and Minor Major Frame Scheduling of Messages High and Low Pri...

Page 14: ...Discrete I O High Level C Software Development Kits with Drivers for Windows Linux and VxWorks Optional Hardware Software Development Kit with PCI Evaluation Board and Design Artifacts see section 2 4...

Page 15: ...O V E R V I E W Data Device Corporation DS BU 67301B G www ddc web com 1 14 6 Figure 1 BU 67301B Total AceXtreme...

Page 16: ...O V E R V I E W Data Device Corporation 7 DS BU 67301B G www ddc web com 1 14 Figure 2 Total AceXtreme Block Diagram...

Page 17: ...ch ever is less V RECEIVER Differential Input Impedance Notes 1 6 3 3V Transformer Coupled 1 0 K Input Voltage Range Threshold Voltage Transformer Coupled 0 86 0 200 14 0 0 860 VPK PK VPK PK Common Mo...

Page 18: ...INT IRDY REQ FRAME TRDY DEVSEL STOP PERR PAR CBEx IOL 8 mA IOH 8 mA JTAG_TDO CPU_STOP_L CPU_RDY_L TXDATA_OUT_x TX_INH_OUT_x USER_OUTPUT_x IOL 4 mA IOH 4 mA CI Input Capacitance All signals except for...

Page 19: ...er Cycle 344 mA 100 Duty Transmitter Cycle 1 8V logic core Note 10 624 160 mA mA POWER DISSIPATION TOTAL HYBRID Note 10 Idle 0 42 W 25 Duty Transmitter Cycle 0 58 W 50 Duty Transmitter Cycle 0 70 W 10...

Page 20: ...Temperature TJ Junction to Ambient JA via simulation 150 C Per JESD 51 2 standard at 25 C JA in Still Air 68 8 C W THERMAL Con t Per JESD 51 6 standard at 25 C JA 1M S 52 9 C W JA 2M S 47 1 C W JA 3M...

Page 21: ...d over the operating range but are not tested 7 Typical value for minimum Intermessage gap time Under software control this may be lengthened to 65 535 s message time in increments of 1 s 8 In 0 5 S i...

Page 22: ...ment Kit for the BU 67301 Total AceXtreme component This kit contains a PCI Evaluation Card to allow easy integration of the BU 67301 component into a standard desktop personal computer The Evaluation...

Page 23: ...ddc web com 1 14 14 CAD Drawing Layout Footprint for Allegro MTBF Prediction Report BC Validation Test Report RT Validation Test Report Product Brief Data Sheet SDK Usage Document SDK Manual Evaluati...

Page 24: ...nsfers and implementing automatic message retries It also includes the capability for automatic bus switchover for failed messages and reporting of various error and status conditions to the host proc...

Page 25: ...automatic boot allowing the Total AceXtreme to respond to commands with Status with its Busy bit set immediately following power turn on without requiring configuration by the host For RT and or Moni...

Page 26: ...g Modes Single Buffer Mode Double Buffer Mode Circular Buffer Mode Global Circular Buffer Command Illegalization by Subaddress Word Count and Mode Codes Programmable Busy by Subaddress Flexible Interr...

Page 27: ...racted from the stored messages IRIG 106 Chapter 10 provides interoperability for such applications as test range telemetry flight test instrumentation mission recorders video data servers surveillanc...

Page 28: ...h either a 48 bit relative or 64 bit absolute time stamp For each message there is also a block status word which includes indications of bus channel and message validity and identifies specific error...

Page 29: ...ular buffer The ADH provides an optional mechanism for moving data from the Total AceXtreme s native data structures and a separate area of Total AceXtreme memory dedicated to the ADH The ADH offers a...

Page 30: ...14 21 Following the issuance of ADH interrupts the host can then transfer data from its ADH memory to designated areas in host space or PCI space memory These transfers may be performed over either t...

Page 31: ...stores time tags associated with all processed MIL STD 1553 messages The Total AceXtreme provides two sources for the relative time tags a local timer with hardware support for the 1553 Synchronize mo...

Page 32: ...These two modes are described below Block Mode Each transfer is initiated by the System Host and is a contiguous block of memory transferred Upstream or Downstream Scatter Gather Mode The DMA Control...

Page 33: ...the Digital I O signals are controllable by means of the Total AceXtreme s Digital I O Register This register also allows the host processor to poll the values of Digital I O signals designated as in...

Page 34: ...reme 1553 core the Total AceXtreme offers low level Built in Test BIST functions that cover the internal memory blocks 1553 core and IRIG module The shared RAM scratchpad RAM and microcode ROM can be...

Page 35: ...L E02 Other values are reserved IDCODE 0b011 The IDCODE for the Total AceXtreme is 0x0590003F HIGHZ 0b010 Sets all the Outputs and Bidirectional Outputs to a high impedance state The HIGHZ can be used...

Page 36: ...are based on three parameters Asynchronous vs Synchronous 32 bit vs 16 bit and non multicast vs multicast address and data buses In Asynchronous mode the host processor does not provide a data transfe...

Page 37: ...he Total AceXtreme s PCI interface Table 3 Total AceXtreme Host Interface Configuration Options Input Signal Name Operation if Logic 1 Operation if Logic 0 PCI_nCPU 32 bit Target Initiator PCI Interfa...

Page 38: ...full transfer cycle For single word Synchronous write transfers CPU_DATA 31 0 CPU_DATA 31 16 or CPU_DATA 15 0 must be presented valid during the same host clock cycle that nDATA_STRB is asserted low...

Page 39: ...ous mode if the Total AceXtreme is the only node on the bus then nSELECT may be tied to logic 0 In Synchronous mode nSELECT must de assert high and remain high for one host clock cycle to end the curr...

Page 40: ...pulse high to latch in the address MEM_nREG and MSW_nLSW for both the first and second 16 bit word transfers In the non Multiplexed mode for the address and data buses ADMULTI 0 ADDR_LAT must be conn...

Page 41: ...11 CPU_WORD_EN 1 0 should be tied to 11 if not used HOST_CLK For the Synchronous interface mode HOST_CLK is used for clocking address data and control issues and for generating the nDATA_RDY nINT and...

Page 42: ...ord Asserts low for single clock cycle Asserts low for single clock cycle For 32 bit Synchronous single word memory read accesses nDATA_RDY asserts low when the Total AceXtreme drives valid data to be...

Page 43: ..._RDY will assert low until one host clock cycle after the host CPU has asserted CPU_nLAST low nINT This is the interrupt request output for the Total AceXtreme s parallel CPU interface The operation o...

Page 44: ...f MSW_nLSW for the most significant word 31 16 is 1 In 16 bit Asynchronous mode TRIG_SEL is used to select which word is transferred first If TRIG_SEL 1 then the upper data word bits 31 16 is transfer...

Page 45: ...CPU RAM 31 16 MSW_nLSW 0 CPU RAM 15 0 1 0 0 MSW_nLSW 1 CPU RAM 31 16 MSW_nLSW 0 CPU RAM 15 0 0 1 1 MSW_nLSW 1 CPU RAM 15 0 MSW_nLSW 0 CPU Buffer 31 16 0 1 0 MSW_nLSW 1 CPU RAM 15 0 MSW_nLSW 0 CPU RAM...

Page 46: ...H O S T I N T E R F A C E Data Device Corporation DS BU 67301B G www ddc web com 1 14 37 Figure 7 32 bit Non Multiplexed Address Asynchronous Interface...

Page 47: ...H O S T I N T E R F A C E Data Device Corporation DS BU 67301B G www ddc web com 1 14 38 Figure 8 32 bit Multiplexed Address Asynchronous Interface...

Page 48: ...H O S T I N T E R F A C E Data Device Corporation DS BU 67301B G www ddc web com 1 14 39 Figure 9 16 bit Non Multiplexed Address Asynchronous Interface...

Page 49: ...H O S T I N T E R F A C E Data Device Corporation DS BU 67301B G www ddc web com 1 14 40 Figure 10 16 bit Multiplexed Address Asynchronous Interface...

Page 50: ...NOTES Timing Characteristics UNITS MIN TYP MAX tSS nSELECT setup time prior to nDATA_STRB low for non multiplexed address or ADDR_LAT high for multiplexed address 0 ns tSH nSELECT hold time following...

Page 51: ...id setup time prior to nDATA_STRB low 10 ns tDH CPU_DATA valid hold time following nDATA_STRB high 0 ns tALP ADDR_LAT pulse width 40 ns For the 32 bit Asynchronous timing diagrams POL_SEL is assumed t...

Page 52: ...CT may be kept low for consecutive transactions by the Total AceXtreme 2 The CPU_WORD_EN 1 0 inputs are used to specify which 16 bit data memory words are valid for this transfer If either or both the...

Page 53: ...onous mode nSELECT may be kept low for consecutive transactions by the Total AceXtreme 2 The CPU_WORD_EN 1 0 inputs are used to specify which 16 bit data memory words are to be written If either or bo...

Page 54: ...hrough the full transfer cycle In Asynchronous mode nSELECT may be kept low for consecutive transactions by the Total AceXtreme 2 For 16 bit accesses CPU_WORD_EN 1 0 must be 11 through the full transf...

Page 55: ...ta transfer nSELECT must be asserted through the full transfer cycle In Asynchronous mode nSELECT may be kept low for consecutive transactions by the Total AceXtreme 2 For 16 bit accesses CPU_WORD_EN...

Page 56: ...y be kept low for consecutive transactions by the Total AceXtreme 2 The CPU_WORD_EN 1 0 inputs are used to specify which 16 bit data memory words are valid for this transfer If either or both these bi...

Page 57: ...e nSELECT may be kept low for consecutive transactions by the Total AceXtreme 2 The CPU_WORD_EN 1 0 inputs are used to specify which 16 bit data memory words are to be written If either or both these...

Page 58: ...ust be asserted through the full transfer cycle In Asynchronous mode nSELECT may be kept low for consecutive transactions by the Total AceXtreme 2 For 16 bit accesses CPU_WORD_EN 1 0 must be 11 throug...

Page 59: ...LECT must be asserted through the full transfer cycle In Asynchronous mode nSELECT may be kept low for consecutive transactions by the Total AceXtreme 2 For 16 bit accesses CPU_WORD_EN 1 0 must be 11...

Page 60: ...tal AceXtreme s HOST_CLK input With sequential burst transfers the host CPU presents its starting address once at the beginning of the transfer Following that a transfer is performed between the host...

Page 61: ...write burst is performed In this example the command FIFO will fill at 80 MHz and drain at 40 MHz for a net fill rate of 40 MHz That is for every two register words written to the FIFO only one is dr...

Page 62: ...he Total AceXtreme will not assert its CPU_nSTOP output However in this case the read transfer will not complete until all of the register write requests are first drained from the FIFO For example if...

Page 63: ...ays a sequential burst read and is therefore read from consecutive addresses The address sampled during the address phase is used as the first address read The Total AceXtreme does not support random...

Page 64: ...PU RAM 15 0 MSW_nLSW 0 CPU RAM 31 16 1 0 MSW_nLSW 1 CPU RAM 15 0 MSW_nLSW 0 CPU RAM 31 16 0 1 MSW_nLSW 0 CPU RAM 15 0 MSW_nLSW 1 CPU RAM 31 16 0 0 MSW_nLSW 0 CPU RAM 15 0 MSW_nLSW 1 CPU RAM 31 16 6 4...

Page 65: ...H O S T I N T E R F A C E Data Device Corporation DS BU 67301B G www ddc web com 1 14 56 Figure 19 32 bit Non Multiplexed Address Synchronous Interface...

Page 66: ...H O S T I N T E R F A C E Data Device Corporation DS BU 67301B G www ddc web com 1 14 57 Figure 20 32 bit Multiplexed Address Synchronous Interface...

Page 67: ...H O S T I N T E R F A C E Data Device Corporation DS BU 67301B G www ddc web com 1 14 58 Figure 21 16 bit Non Multiplexed Address Synchronous Interface...

Page 68: ...H O S T I N T E R F A C E Data Device Corporation DS BU 67301B G www ddc web com 1 14 59 Figure 22 16 bit Multiplexed Address Synchronous Interface...

Page 69: ...5 Non Multiplexed 16 Read Memory Figure 26 Non Multiplexed 16 Read Register Figure 27 Non Multiplexed 16 Write Memory Figure 28 Non Multiplexed 16 Write Register Figure 29 Multiplexed 32 Read Memory F...

Page 70: ...r Multiplexed 32 bit or 16 bit Random Memory or Register Read Not Supported Table 11 Synchronous Timing Parameters REF DESCRIPTION NOTES Timing Characteristics UNITS MIN TYP MAX fCLK HOST_CLK frequenc...

Page 71: ...load 2 6 8 ns tLS CPU_nLAST setup time NOTE 4 ns tLH CPU_nLAST hold time NOTE 0 ns tSHC nSELECT hold cycle time NOTE tCLK ns Note Indicated times are relative to the rising edge of HOST_CLK For the 3...

Page 72: ...2 The CPU_WORD_EN 1 0 inputs are used to specify which 16 bit data memory words are valid for this transfer If either or both these bits is 0 then the corresponding 16 bit word s will return a value o...

Page 73: ...transfer cycle and de asserted high at the end of the transfer 2 For register transfers the value of the CPU_WORD_EN 1 0 inputs must be 11 3 For a single word register read access CPU_nSTOP asserts lo...

Page 74: ...used to specify which 16 bit data memory words are to be written If either or both these bits is 0 then the corresponding 16 bit word s will not be written to Total AceXtreme memory These inputs shoul...

Page 75: ...nd de asserted high at the end of the transfer 2 For 16 bit accesses CPU_WORD_EN 1 0 must be 11 through the full transfer cycle 3 Unless the Total AceXtreme command FIFO is full CPU_nSTOP will not be...

Page 76: ...end of the transfer 2 For 16 bit accesses CPU_WORD_EN 1 0 must be 11 through the full transfer cycle 3 For a register read access CPU_nSTOP asserts low simultaneous with nDATA_RDY and de asserts high...

Page 77: ...ansfer cycle and de asserted high at the end of the transfer 2 For 16 bit accesses CPU_WORD_EN 1 0 must be 11 through the full transfer cycle 3 Unless the Total AceXtreme command FIFO is full CPU_nSTO...

Page 78: ...ransfer cycle and de asserted high at the end of the transfer 2 For 16 bit accesses CPU_WORD_EN 1 0 must be 11 through the full transfer cycle 3 Unless the Total AceXtreme command FIFO is full CPU_nST...

Page 79: ...PU_WORD_EN 1 0 inputs are used to specify which 16 bit data memory words are to be read for this transfer If either or both these bits is 0 then the corresponding 16 bit word s will return a value of...

Page 80: ...sfer cycle and de asserted high at the end of the transfer 2 For register accesses the value of the CPU_WORD_EN 1 0 inputs must be 11 3 For a register read access CPU_nSTOP asserts low simultaneous wi...

Page 81: ...s are used to specify which 16 bit data memory word s are to be written If either or both these bits is 0 then the corresponding 16 bit word s will not be written These inputs should be tied high if u...

Page 82: ...the end of the transfer 2 For 16 bit accesses CPU_WORD_EN 1 0 must be 11 through the full transfer cycle 3 Unless the Total AceXtreme command FIFO is full CPU_nSTOP is not asserted for memory accesse...

Page 83: ...r 16 bit accesses CPU_WORD_EN 1 0 must be 11 through the full transfer cycle 3 For a register read access CPU_nSTOP asserts low simultaneous with nDATA_RDY and de asserts high on the host clock cycle...

Page 84: ...rted high at the end of the transfer 2 For 16 bit accesses CPU_WORD_EN 1 0 must be 11 through the full transfer cycle 3 Unless the Total AceXtreme command FIFO is full CPU_nSTOP is not asserted for wr...

Page 85: ...erted high at the end of the transfer 2 For 16 bit accesses CPU_WORD_EN 1 0 must be 11 through the full transfer cycle 3 Unless the Total AceXtreme command FIFO is full CPU_nSTOP is not asserted for w...

Page 86: ...e following CPU_nLAST asserting low the last word is removed tri stated from the data bus and nDATA_RDY is de asserted high At this time or later nSELECT must be de asserted high completing the burst...

Page 87: ...PU_nLAST asserting low the Total AceXtreme reads the last word from the data bus and nDATA_RDY is de asserted high At this time or later nSELECT must be de asserted high completing the burst write tra...

Page 88: ...the last word from the data bus and nDATA_RDY is de asserted high At this time or later nDATA_STRB and nSELECT must be de asserted high completing the burst write transfer 2 The CPU_WORD_EN 1 0 input...

Page 89: ...PU_nLAST must be asserted high until the last 16 bit word is to be read On the rising clock edge following CPU_nLAST asserting low the last 16 bit word is removed tri stated from the data bus and nDAT...

Page 90: ...presented initiates the sequential burst write transfer nSELECT must be asserted low through the full burst cycle The nDATA_RDY output is initially asserted low on the clock cycle prior to the cycle i...

Page 91: ...RB and nSELECT must be asserted low through the entire time of the transfer The nDATA_RDY output is initially asserted low on the clock cycle prior to the cycle in which the Total AceXtreme reads the...

Page 92: ...valid data word on the data bus CPU_nLAST must be asserted high until the last word is to be read On the rising host clock edge following CPU_nLAST asserting low the last word is removed tri stated f...

Page 93: ...low while nSELECT remains asserted low initiates the sequential burst transfer nSELECT must be asserted low through the remainder of the burst cycle The nDATA_RDY output is initially asserted low on t...

Page 94: ...burst One clock cycle later a one clock cycle wide pulse of nDATA_STRB low while nSELECT remains asserted low initiates the sequential burst transfer nSELECT must be asserted low through the remainder...

Page 95: ...rior to the cycle in which the Total AceXtreme reads the first 16 bit data word from the data bus CPU_nLAST must be asserted high until the last 16 bit word is to be written On the rising clock edge f...

Page 96: ..._nSTOP output low If this occurs it is recommended for the host to delay before attempting to retry the current multi word transfer To ensure that the FIFO has drained sufficiently the host should del...

Page 97: ...Total AceXtreme and Total AceXtreme to host PCI Initiator DMA Engine Data Transfer Modes Block transfer mode single descriptor execution via registers Scatter gather mode descriptors stored in host me...

Page 98: ...32 bit writes to memory 8 bit memory writes are not supported Reads from memory BAR0 will ignore byte lanes because reads are non destructive and cause no state change to the circuit This allows for a...

Page 99: ...H O S T I N T E R F A C E Data Device Corporation DS BU 67301B G www ddc web com 1 14 90 Figure 48 Interface Between Host PCI Bus and Total AceXtreme PCI Signal List...

Page 100: ...rced by the active target upon decoding that its address and bus commands are valid STOP I O PCI Stop This signal indicates the current target is requesting the master to stop the current transaction...

Page 101: ...Total AceXtreme s PCI Target interface 6 5 4 1 PCI Target STOP Assertion Similar to the Synchronous parallel CPU interface the Total AceXtreme posts all requests to read or write individual words on t...

Page 102: ...to TRDY delay for a slave write cycle 66MHz or 33MHz 5 tCLK 50 6 tCLK 75 ns tDMA_START Falling edge of TRDY for the write to start the DMA to the falling edge of REQ for the first DMA transfer 66MHz...

Page 103: ...TART the delay from the end of the host write to the Total AceXtreme s PCI Target interface falling edge of TRDY to the falling edge of the Total AceXtreme s REQ output By asserting REQ the Total AceX...

Page 104: ...ddc web com 1 14 95 Figure 52 PCI DMA Start Delay Figure 53 PCI DMA Burst Write TRDY DEVSEL IRDY C BE 3 0 FRAME tCLK AD 31 0 HOST_CLK REQ Address 0x7 Data 0x0 tDMA_Start TRDY DEVSEL IRDY C BE 3 0 FRA...

Page 105: ...I N T E R F A C E Data Device Corporation DS BU 67301B G www ddc web com 1 14 96 Figure 54 PCI DMA Burst Read TRDY DEVSEL IRDY C BE 3 0 FRAME tCLK AD 31 0 HOST_CLK REQ GNT Data Data Data Address 0xE 0...

Page 106: ...um o 2 0 1uF Ceramic Chip o 6 0 01uF Ceramic Chip For 1 8V_PLL 1 ball o 1 0 1uF Ceramic Chip o 1 0 01uF Ceramic Chip In order to minimize power supply noise on the PLL supply pin DDC recommends the us...

Page 107: ...for the 40 MHz CLK_IN clock to be stable and to assert the nPOR input to logic 0 Asserting nPOR low is necessary to ensure the correct initialization of the Total AceXtreme 4 Following a minimum of 1...

Page 108: ...P O W E R I N P U T S Data Device Corporation DS BU 67301B G www ddc web com 1 14 99 Figure 56 Power Up Initialization Sequence Timing...

Page 109: ...xternal signals to specific pins The user has the option of connecting them on the PC board as shown in Figure 58 or connecting the 1553 Core interface signals to an external Transceiver If the intern...

Page 110: ...For these applications a transceiver providing an approximate sinusoidal waveform with reduced harmonic content rather than a trapezoidal waveform must be used In addition the McAir standards require...

Page 111: ...the internal transceivers and transformers it is possible to use Total AceXtreme with external electrical MIL STD 1553 transceivers or with fiber optic transceivers Figure 60 illustrates the interface...

Page 112: ...M I L S T D 1 5 5 3 T R A N S C E I V E R O P T I O N S Data Device Corporation DS BU 67301B G www ddc web com 1 14 103 Figure 60 Total AceXtreme Interface to Fiber Optic Transceivers...

Page 113: ...purpose of this ground thermal plane is to conduct the heat being generated by the transceivers within the package and conduct this heat away from the Total AceXtreme In general the circuit ground and...

Page 114: ...T P JB 0 42 46 9 0 19 7 C In order to maintain a junction temperature below 135 C the case temperature must be kept below 115 C If operation with a package temperature of 125 is required then a heatsi...

Page 115: ...eptable operating temperature for a given application It is possible to obtain a more accurate estimate of the acceptable operating temperature by performing a more accurate simulation of the heat flo...

Page 116: ...transactions addresses on the CPU bus The entire memory range 256 KBytes is accessible through the Host interface 10 2 Register Address Space Total AceXtreme registers are accessible from both the PC...

Page 117: ...et following power turn on If nRTBOOT is hardwired to logic 1 the Total AceXtreme will initialize in either Idle mode for an RT only part or BC mode for a BC RT MT part nPOR C10 None Power on Reset As...

Page 118: ...nstruction register JTAG_TDO O B8 N A This ball is the serial test data output Outputs serial data which comes from either the test data registers or instruction register JTAG_nTRST I B9 50k Pullup Th...

Page 119: ...ore data phases Address phases are identified when the control signal FRAME is asserted Data transfers occur during those clock cycles in which the control signals IRDY and TRDY are both asserted PCI_...

Page 120: ...equest to the bus master to stop the current transaction IRDY I O C3 None Initiator Ready This signal is sourced by the bus master and indicates that the bus master is able to complete the current dat...

Page 121: ...rrors data parity errors on Special Cycle commands or any other condition having a catastrophic system impact INTA O A9 None Interrupt A This pin is a level sensitive active low interrupt to the host...

Page 122: ...None CPU_DATA 10 I O K2 None CPU_DATA 09 I O M1 None CPU_DATA 08 I O N2 None CPU_DATA 07 I O N3 None CPU_DATA 06 I O N4 None CPU_DATA 05 I O M4 None CPU_DATA 04 I O K3 None CPU_DATA 03 I O M5 None CP...

Page 123: ...ltiplexed asynchronous mode nDATA_STRB must be asserted throughout each 32 bit or 16 bit data transfer until nDATA_RDY is asserted For multiplexed asynchronous mode nDATA_STRB must be asserted followi...

Page 124: ...e is 0 If POL_SEL is 0 then RD_nWR has inverted polarity i e read is 0 and write is 1 In 16 Bit Mode POL_SEL indicates which word is the most significant word If POL_SEL is 0 then the least significan...

Page 125: ...cycle Not used in asynchronous mode CPU_WORD_EN 1 I P4 50k Pullup Signal s should be active throughout the entire transfer cycle 32 Bit Mode Input to specify which input 16 bit data words are valid fo...

Page 126: ...ernal RT address latch If RT_AD_LAT is logic 0 then the Total AceXtreme internal RT Address will continuously track inputs RTAD4 RTAD0 and RTADP When a logic 1 level is applied to the RT_AD_LAT input...

Page 127: ...ition of nPOR following power up A logic 1 input disables both the power up and user initiated automatic BIST TX_INH_A I P13 50k Pullup Transmitter inhibit inputs for Channel A and Channel B MIL STD 1...

Page 128: ...Maxim MAX6642 temperature sensor chip http pdfserv maxim ic com en ds MAX6642 pdf or equivalent The cathode is tied to ground internally EXT_TRIG I T11 50k Pullup BC External Trigger EXT_TRIG may be u...

Page 129: ...Transceiverless operation Digital Manchester bi phase transmit data outputs Connect directly to corresponding inputs of a MIL STD 1553 or MIL STD 1773 fiber optic transceiver TXDATA_IN_A_L I K11 50k P...

Page 130: ...ect directly to corresponding outputs of a MIL STD 1553 or MIL STD 1773 fiber optic transceiver RXDATA_OUT_A O K8 N A RXDATA_IN_A_L I These two signals MUST be directly connected for normal Built In t...

Page 131: ...Power and Ground Connections Signal Name BALL Description 3 3V_LOGIC C4 C5 C6 C7 C8 C9 H4 H5 H6 H7 H8 H9 C12 D10 M7 3 3V Protocol VDD I O Supply Voltage 1 8V_CORE E5 E6 E7 F5 F6 F7 F8 1 8V Protocol Co...

Page 132: ...3 A16 A17 A18 B1 B2 B15 B16 B17 B18 C1 C15 C16 C17 C18 D15 D16 E15 E16 F15 F16 G15 G16 H15 H16 H17 H18 J15 J16 J17 J18 K15 K16 K17 K18 L15 L16 L17 L18 M15 M16 M17 M18 N11 N12 N15 N16 P15 P16 R15 R16 T...

Page 133: ...INTA G9 GND_LOGIC N9 3 3V_XCVR A10 JTAG_TMS G10 RTAD2 N10 NC A11 GND_LOGIC G11 RT_AD_LAT N11 NC A12 GND_LOGIC G12 RTAD3 N12 NC A13 PLL_LOCKED G13 RTAD1 N13 TAG_ENABLE A14 GND_LOGIC G14 RTAD0 N14 IRIG...

Page 134: ...OGIC J6 RD_nWR R6 GND_XCVR C7 3 3V_LOGIC J7 CPU_ASYNC_nSYNC R7 GND_XCVR C8 3 3V_LOGIC J8 RXDATA_IN_A R8 GND_XCVR C9 3 3V_LOGIC J9 RXDATA_IN_A_L R9 GND_XCVR C10 nPOR J10 TXDATA_OUT_A R10 NC C11 PCI_nCP...

Page 135: ...2 L2 PAR CPU_ADDR 04 U2 NC E3 PCI_AD 21 CPU_DATA 21 L3 PCI_AD 11 CPU_DATA 11 U3 NC E4 GND_LOGIC L4 PCI_AD 02 CPU_DATA 02 U4 NC E5 1 8V_CORE L5 PCI_AD 00 CPU_DATA 00 U5 NC E6 1 8V_CORE L6 MSW_nLSW U6 R...

Page 136: ...F6 1 8V_CORE M6 nDATA_STRB V6 RXDATA_OUT_B F7 1 8V_CORE M7 3 3V_LOGIC V7 RXDATA_OUT_B_L F8 1 8V_CORE M8 NC V8 NC F9 GND_LOGIC M9 TXDATA_IN_B_L V9 NC F10 GND_LOGIC M10 TXDATA_IN_B V10 GND_XCVR F11 GND_...

Page 137: ...GND_ LOGIC 1 8V PLL 1 8V CORE GND_ LOGIC 3 3V LOGIC RXDATA _IN_A RXDATA _OUT_A TRIG_ SEL NC 3 3V XCVR GND_ XCVR GND_ XCVR 3 3V XCVR NC NC 8 7 JTAG TCK PCIREQ CPU_ADD R 12 3 3V LOGIC GND_ LOGIC 1 8V C...

Page 138: ...Data Device Corporation 129 DS BU 67301B G www ddc web com 1 14 12 MECHANICAL OUTLINE Figure 62 Total AceXtreme Mechanical Outline Drawing...

Page 139: ...equirements at high transmit duty cycles 3 Unless otherwise specified these products contain tin lead solder BU 67301E0T0R JL0 Hardware Software Development Kit Optional PCI Evaluation Board with Cabl...

Page 140: ...for our card level products All of our Synchro Resolver line is supported by software designed to meet today s COTS MOTS needs The Synchro Resolver line has been field proven for military and industri...

Page 141: ...onics K K Dai ichi Magami Bldg 8F 1 5 Koraku 1 chome Bunkyo ku Tokyo 112 0004 Japan Tel 81 3 3814 7688 Fax 81 3 3814 7689 Web site www ddcjapan co jp Asia Data Device Corporation RO Registered in Sing...

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