DDC Total-AceXtreme BU-67301B, Design Manual

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O V E R V I E W
Data Device Corporation DS-BU-67301B-G
www.ddc-web.com 1/14
10
Table 1. Total-AceXtreme® Series Specifications
PARAMETER MIN TYP MAX UNITS
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
• Logic +3.3V (V
DDIO
)
• Logic +3.3V (V
DDIO
) Ramp Rate
3.0 3.3 3.6
1.85
V
V/µs
• Core and PLL +1.8V (V
CORE
and V
PLL
)
• Core and PLL +1.8V (V
CORE
and V
PLL
) Ramp Rate
1.65 1.8 1.95
1.85
V
V/µs
• Transc3.3V 3.135 3.3 3.465 V
Current Drain (Total Hybrid) (Note 10)
3.3V (I/O and transceiver) (Note 10):
• Idle — — 40 mA
• 25% Duty Transmitter Cycle — — 214 mA
• 50% Duty Transmitter Cycle — — 344 mA
• 100% Duty Transmitter Cycle
1.8V (logic core) (Note 10)
—
—
—
—
624
160
mA
mA
POWER DISSIPATION: TOTAL HYBRID (Note 10)
• Idle — — 0.42 W
• 25% Duty Transmitter Cycle — — 0.58 W
• 50% Duty Transmitter Cycle — — 0.70 W
• 100% Duty Transmitter Cycle — — 0.90 W
POWER DISSIPATION: TRANSCEIVER CHIP (Note 10)
• Idle — — 0.09 W
• 25% Duty Transmitter Cycle — — 0.23 W
• 50% Duty Transmitter Cycle — — 0.33 W
• 100% Duty Transmitter Cycle — — 0.50 W
CLOCK INPUTS
PCI CLOCK INPUT FREQUENCY
0 — 66 MHz
HOST_CLK (CPU) CLOCK INPUT FREQUENCY
0 — 80 MHz
CLOCK_IN (MIL-STD-1553) FREQUENCY
• Nominal Value — 40 — MHz
Long Term Tolerance
• 1553A Compliance 0.01 — -0.01 %
• 1553B Compliance 0.10 — -0.10 %
Short Term Tolerance, 1 second
• 1553A Compliance -0.001
—
0.001 %
• 1553B Compliance -0.01
—
0.01 %
Duty Cycle 40
—
60 %
Jitter Tolerance —
—
100 Ps