T O T A L - A C E X T R E M E ® S I G N A L S
Data Device Corporation
DS-BU-67301B-G
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Table 21. Miscellaneous Signals
Signal Name
BALL
Pullup/
Pulldown
Description
HOST_CLK/PCI_CLK (I)
F2
None
HOST/PCI Clock.
Input clock from the PCI Bus or host processor. All input signals: address, data
and control must meet the setup and hold time requirements relative to this
clock signal. All output data and control propagation delay (8 ns max) will be
referenced to this input clock. The input clock is designed to run up to 80-MHz
(12.5 ns period) in CPU mode and up to 66-MHz (15.0 ns period) in PCI mode.
USER_OUTPUT_1 (O)
T13
N/A
Represents the status of bits 18 & 17 of “GBL_CFG” (Global Configuration)
Register.
When bit 18 is set to ‘1’, USER_OUTPUT_1 is driven to a logic high. When
‘0’, USER_OUTPUT_1 will be driven to a logic low.
When bit 17 is set to ‘1’, USER_OUTPUT_2 is driven to a logic high. When
‘0’, USER_OUTPUT_2 will be driven to a logic low.
USER_OUTPUT_2 (O)
U13
N/A
TEMP_DIODE
E13
N/A
Anode of integrated diode for measurement of junction temperature.
The Total-AceXtreme incorporates a temperature measurement into the MIL-
STD-1553 Protocol ASIC. The junction temperature may be measured and
digitized using a Maxim MAX6642 temperature sensor chip
(http://pdfserv.maxim-ic.com/en/ds/MAX6642.pdf) or equivalent. The cathode
is tied to ground internally.
EXT_TRIG (I)
T11
50k Pullup
BC External Trigger.
EXT_TRIG may be used to synchronize BC operation to an external source.
Can be used to start the operation of the BC Command Interpreter, or can be
used to have the BC wait at specific points in the Instruction List for an
external synchronization.
In BC mode, during the execution of a Wait for External Trigger (WTG)
instruction, the Total-AceXtreme BC will wait for a low-to-high transition on
EXT_TRIG before proceeding to the next instruction.
EXT_TRIG is a rising edge sensitive signal that must not violate a minimum
pulse width of 100ns to ensure proper sampling.
nSSFLAG (I)
R14
50k Pullup
Subsystem Flag (RT Mode only)
In Single-RT mode, if this input is asserted low, the Subsystem Flag bit will be
set in the Total-AceXtreme’s RT Status Word.
If the nSSFLAG input is logic ‘0’ while bit 7 of the “RT Status Input Control”
register has been programmed to logic ‘1’ (cleared), the Subsystem Flag RT
Status Word bit will become logic "1," but bit 7 of the “RT Status Input Control”
register, will return logic ‘1’ when read. That is, the logic sense provided to the
nSSFLAG input has no effect on the value of the SUBSYSTEM FLAG register
bit.
In BC, Multi-RT, and Monitor (only) modes, the nSSFLAG input is not used
and should be connected to logic ‘1’.
