Document Number: 002-10689 Rev *H
Page 74 of 166
S6J32E, S6J32F, S6J32G Series
8.3.2
Power Supply Current
8.3.2.1
Run Mode
Symbol
Pin Name
Conditions
Value
Unit
T
A
(
o
C)
Remark
Typ
Max
I
CC5
VCC5
Normal Operation
45
-
mA
25
-
-
70
mA
105
Adder for Work Flash Programming or
Erasing
-
20
mA
105
-
I
CC12
VCC12
CPU: 240 MHz, HPM: 120 MHz, GDC:
200 MHz (Worst case use case)
700
-
mA
25
*2
-
1250
mA
105
*2
CPU: 120 MHz, HPM: 60 MHz, GDC: 0 MHz
For TC Flash Programming or Erasing
(Worst case use case)
-
900
mA
105
*2
CPU: 80 MHz, HPM: 40 MHz, GDC: 0 MHz
For TC Flash Programming or Erasing
Worst case use case
-
800
mA
105
*2
Example use case *3
-
635
mA
105
*3
Adder for Work Flash Programming or
Erasing
-
20
mA
105
-
ILVDS
VCC3_LVDS_Tx
50 MHz
-
75
mA
105
*1
AVCC3_LVDS_PLL
50 MHz
-
9
mA
105
-
Notes:
−
The output port current is not included in the specified value
−
*1. A few mA, which depend on usage for FPD-Link data transfer, should be estimated for each port in an actual application,
and then it should be added to the current consumption at VCC3_LVDS_Tx.
−
The current consumption at VCC3_LVDS_Tx is specified under RL= 100 ohm, CL= 5 pF, f = 50 MHz, and 0/1 alternation
pattern output.
−
*2 This current consumption assumes extremely high activity, which is unlikely to achieved in real application. Actual current
consumption is dependent on actual application.
−
*3 Example use case at following conditions
CPU: 240 MHz, HPM: 120 MHz, GDC: 200 MHz
(Clock settings according to ch 8.4.3 Internal Clock Timing Max*1)
Active peripherals: Ethernet, 1ch HyperBus (Flash+RAM), PWMs, ADC, 6ch SMCs, I2C, 2ch CAN, 2ch LIN and 2ch SPI
DMAC active (WorkFlash > SystemRAM), All timers active
CPU: Arm Cortex R5_max_power function
GFX-Sub system:
Blit Engine with 3 (= all) source buffers active (ROP3, noise RGBA, 32 bpp)
Both Display Controllers with 7 display buffers active (noise RGBA, 32 bpp)
Drawing Engine and Command Sequencer active, Capture controller idle
Display Controller #1 : 10 MHz RGB interface
Display Controller #2 : 22 MHz FPD link
I/Os do no toggle